1. EE534 VLSI Design System Summer Lecture 12:Chapter 7 &9 Transmission gate and Dynamic logic circuits design approaches

2. Review: Fan-In ConsiderationsB C D CL A C3 B
Distributed RC model
(Elmore delay)
TpHL=0.69[R1C1+(R1+R2)C2+(R1+R2+R3)C3+(R1+R2+R3+R4)CL]
tpHL = 0.69 Reqn(C1+2C2+3C3+4CL)
Propagation delay deteriorates rapidly as a function of fan-in – quadratically in the worst case.
While output capacitance makes full swing transition (from VDD to 0), internal nodes only transition from VDD-VTn to GND
C1, C2, C3 (from junction capacitances as well as the gate-to-source and gate-to-drain capacitances (turned into capacitances to ground using the Miller effect)) on the order of 0.85 fF for W/L of 0.5/0.25 NMOS and 0.375/0.25 PMOS, CL of 3.47 fF with NO output load (all diffusion capacitance – intrinsic capacitance of the gate itself).
To give a 85 psec tpHL (simulated as 86 psec).
The simulated worst case low-to-high delay was 106 ps. C2 C C1 D

3. Review: tp as a Function of Fan-In
quadratic function of fan-in
tp (psec)
tpHL tp
Fixed fan-out (NMOS 0.5 micron, PMOS 1.5 micron)
tpLH increases linearly due to the linearly increasing value of the diffusion capacitance of the pmos transistors (resistance remains unchanged)
tpHL increase quadratically due to the simultaneous increase in pull-down resistance and internal capacitance
tpLH
linear function of fan-in
fan-in
Gates with a fan-in greater than 4 should be avoided.

4. Review: Influence of Fan-In and Fan-Out on Delay
Fan-out: Number of Gates connected to the output
in static CMOS, there are two gate capacitances per Fan-out
Fan-in: Number of independent variables for the logic function, which has a quadratic effect on tp due to:
resistance increasing
capacitance increasing V DD A B C D C D

5. Fast Complex Gates: Design Technique 1
Transistor sizing
as long as fan-out capacitance dominates
Progressive sizing
Distributed RC line
M1 > M2 > M3 > … > MN
(the MOSFET closest to the output should be the smallest) CL
InN MN
With transistor sizing, if the load capacitance is dominated by the intrinsic capacitance of the gate, widening the device only creates a “self loading” effect and the propagation delay is unaffected (and may even become worse).
For progressive sizing, M1 have to carry the discharge current from M2 (C1), M3 (C2), … MN and CL so make it the largest. MN only has to discharge the current from MN (CL)(no internal capacitances).
While progressive sizing is easy in a schematic, in a real layout it may not pay off due to design-rule considerations that force the designer to push the transistors apart, increasing internal capacitance. C3
In3 M3 C2
In2 M2
Can reduce delay by more than 20%; decreasing gains as technology shrinks C1
In1 M1
Resistance of M1(R1) N times in the delay
Equation. The resistance of M2(R2) appears N-1 times etc.

6. Review : Fast Complex Gates: Design Technique 2
Input re-ordering
when not all inputs arrive at the same time
critical path
critical path
01 CL CL
charged
charged 1
In1
In3 M3 M3
For lecture.
Critical input is latest arriving signal – the path through the logic that determines the ultimate speed of the structure is called the critical path.
Place latest arriving signal (critical path) closest to the output can result in a speed up. 1 C2 1 C2
In2
In2 M2
discharged M2
charged 1 C1 C1
In3
discharged
In1
charged M1 M1
01
delay determined by time to discharge CL, C1 and C2
delay determined by time to discharge CL

7. Review: Sizing and Ordering EffectsB C D 3 3 3 3 CL A 4 4
= 100 fF C3 B 4 5
Progressive sizing in pull-down chain gives up to a 23% improvement.
Input ordering saves 5%
critical path A – 23% C2 C 4 6 C1 D 4 7

8. Review: Fast Complex Gates: Design Technique 3
Alternative logic structures
F = ABCDEFGH
Reduced fan-in -> deeper logic depth
Reduction in fan-in offsets, by far, the extra delay incurred by the NOR gate (second configuration).
Only simulation will tell which of the last two configurations is faster, lower power
Need to run the simulations to get real timing numbers – and power

9. Ratioed Logic Ratioed logic is an attempt to reduce
The number of transistors required to implant a given logic function, often at the cost of reduced robustness and extra power dissipation

10. Ratioed Logic

11. Review: Load Lines of Ratioed Gates

12. Other logic styles Transmission gate logic Pass-transistor logic
NMOS transistors used as switches
Other variants:
Complementary pass-transistor logic (CPL)
Swing-restored pass-transistor logic

13. Transmission Gate Logic= =
NMOS and PMOS connected in parallel
Allows full rail transition – ratioless logic
Equivalent resistance relatively constant during transition
Complementary signals required for gates
Some gates can be efficiently implemented using transmission gate logic

14. Transmission Gates (pass gates)
Use of transistors as switches are called transmission gates because switches can transmit information from one circuit to another.

15. CMOS Transmission Gate
A CMOAS transmission gate can be constructed by parallel combination of NMOS and PMOS transistors, with complementary gate signals.
The main advantage of the CMOS transmission gate compared to NMOS transmission gate is to allow the input signal to be transmitted to the output without the threshold voltage attenuation.
CMOS transmission gate

16. Characteristics of a CMOS Transmission gate
Case I:
If  =VDD, , VI=VDD, and VO is initially zero.
In NMOS transistor, under above Condition, terminal ‘a’ acts as the drain and terminal ‘b’ acts as the source.
For the PMOS, device terminal ‘c’ acts as the drain and terminal ‘d’ acts as the source. In order to charge the load capacitor, current enters the NMOS drain and the PMOS source. The NMOS gate to source voltage is,
VGSN =  - VO = VDD - VO
this implies that VGSN continuously change.
And for PMOS source-to-gate voltage is
VGSP = VI -  = VDD – 0 = VDD
This implies that VGSP remains constant.
Charging path
Drain
source

17. Characteristics of a CMOS Transmission gate (Cont.)
When VO=VDD-VTN, VGSN=VTN,
the NMOS transmission gate cuts
off and IDN=0.
However, PMOS transistor continue to conduct, because VGSP of the PMOS is a constant
(VGSP=VDD). In PMOS transistor
IDP=0, when VSDP=0, which would be
possible only, if,
VO = VI = 5V
This implies that a logic ‘1’ is transmitted unattenuated through
the CMOS transmission gate in contrast to the NMOS transmission
gate.
NMOS transmission gate

18. Characteristics of a CMOS Transmission gate (Cont.)
Case II:
If VI = 0,  = VDD, VO=VDD initially.
terminal ‘a’ acts as a source and terminal
‘b’ acts as a drain.
For the PMOS transistor terminal
‘c’ acts as a source and terminal ‘d’ acts as a drain.
In order to discharge the capacitors current enter the NMOS drain and PMOS source. The NMOS gate to source voltage is,
And PMOS source to gate voltage is
When VSGP=VO=|VTP|, PMOS transistor cutoff and iDP=o
However, since VGSN=VDD, the NMOS transistor continue
conducting and capacitor completely discharge to zero.
Finally, VO=0, which is a good logic 0.
discharging path
source
drain
drain
source

19. Equivalent Resistance Model
For a rising transition at the output (step input)
NMOS sat, PMOS sat until output reaches |VTP|
NMOS sat, PMOS lin until output reaches VDD-VTN
NMOS off, PMOS lin for the final VDD – VTN to VDD voltage swing

20. Equivalent Resistance – Region 1
NMOS sat:
PMOS sat:
NMOS sat, PMOS sat until output reaches |VTP| because drain to source voltage is still high

21. Equivalent Resistance – Region 2
NMOS sat:
PMOS lin:
NMOS sat, PMOS lin until output reaches VDD-VTN

22. Equivalent Resistance – Region 3
NMOS off:
PMOS lin:
NMOS off, PMOS lin for the final VCC – VTN to VCC voltage swing

23. Equivalent resistance
Equivalent resistance Req is parallel combinaton of Req,n and Req,p
Req is relatively constant
This property of CMOS TG is quite desirable

24. TG equivalent resistor model

25. Delay in Transmission Gate Networks

26. Delay Optimization
Example: 16 cascade minimum size transmission gates with resistance of 8K
C=3.6fF for low to high transition. The delay is given by
Use of long pass transistors chains causes significant delay degradation
What could be the possible solution to minimize this delay?

27. Break the chain and insert buffers
The insertion of the buffer inverters reduces the delay by a factor of almost 2

28. CMOS transmission gate remains in a dynamic condition.
If VO=VDD, then NMOS substrate to terminal ‘b’ pn junction is reverse biased and capacitor CL can discharge.
If VO=0, then the PMOS terminal c-to-substrate pn junction is reverse biased and capacitance CL can be charge to a positive voltage.
This implies that the output high or low of CMOS transmission gate circuit do not remain constant with time (dynamic behavior).

29. Dynamic CMOS Advantages: Faster – why? Reduced input load
No switching contention
Less layout area
Disadvantages:
Charge leakage
Charge sharing
Capacitive coupling
Cannot be cascaded
Complicated timing/clocking
Higher power
Lower noise margins
clk
NMOS network
clk
Gnd
These issues are discussed in chapter 9

30. TG Applications: Multiplexer (MUX) circuit
Case I: When the input S is logic high
Bottom transistor is conducting and output is equal to input B
Case II: When the input S is logic low
Bottom Tg turn off and top TG turn on and output is equal to input A

31. TG Multiplexer S In2 S F In1 S F = !(In1  S + In2  S) S S F VDD GND
How does this compare to a static complementary multiplexer (4t in pull down, 4t in pull up), so 2 fewer transistors.
Smaller - probably
Faster?
Cooler?
In1 S
F = !(In1  S + In2  S)
GND
In1 S S
In2

32. Transmission Gate XOR B B M2 A A F M1
M3/M4 B B

33. Carry is the critical signal:
Example: Full Adder
Carry is the critical signal:
closest to the output

34. A Revised Adder Circuit: applying the design techniques to reduce area and delay

35. TG Full Adder Cin B A Sum Cout 16 transistors – vesterbacke in SiPS99
no more than 2 PT in series, max
full swing - tranmission gates

36. Transmission Gate Full Adder
Similar delays for sum and carry

37. Chapter 9 Dynamic logic circuits design

38. Dynamic CMOS
In static circuits at every point in time (except when switching) the output is connected to either GND or VDD via a low resistance path.
fan-in of n requires 2n (n N-type + n P-type) devices
Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes.
requires on n + 2 (n+1 N-type + 1 P-type) transistors

39. Static vs Dynamic Storage
Static storage
preserve state as long as the power is on
have positive feedback (regeneration) with an internal connection between the output and the input
useful when updates are infrequent (clock gating)
Dynamic storage
store state on parasitic capacitors
only hold state for short periods of time (milliseconds)
require periodic refresh
usually simpler, so higher speed and lower power
clock gating - conditional clocks - where the clock is turned off for unused modules to save on power

40. Evolution from static to dynamic logic gate

41. Dynamic CMOS Advantages: Faster – why? Reduced input load
No switching contention
Less layout area
Disadvantages:
Charge leakage
Charge sharing
Capacitive coupling
Cannot be cascaded
Complicated timing/clocking
Higher power
Lower noise margins
clk
NMOS network
clk
Gnd

42. Dynamic Gate Two phase operation Precharge (CLK = 0)
Out
Clk A B C Mp Me
Clk Mp
Out CL
In1
In2
PDN
For class handout
In3
Clk Me
Two phase operation
Precharge (CLK = 0)
Evaluate (CLK = 1)

43. Dynamic Gate Two phase operation Precharge (Clk = 0)
Out
Clk A B C Mp Me
off
Clk Mp on 1
Out CL
((AB)+C)
In1
In2
PDN
For lecture
Evaluate transistor, Me, eliminates static power consumption
In3
Clk Me
off on
Two phase operation
Precharge (Clk = 0)
Evaluate (Clk = 1)

44. Inputs to the gate can make at most one transition during evaluation.
Conditions on Output
Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation.
Inputs to the gate can make at most one transition during evaluation.
Output can be in the high impedance state during and after evaluation (PDN off), state is stored on CL
This behavior is fundamentally different than the static counterpart that always has a low resistance path between the output and one of the power rails.
This behavior is fundamentally different than the static counterpart that always has a low resistance path between the output and one of the power rails.

45. Properties of Dynamic CMOS Gates
Logic function is implemented by the PDN only
number of transistors is N + 2 (versus 2N for static complementary CMOS)
Full swing outputs (VOL = GND and VOH = VDD)
Non-ratioed - sizing of the devices does not affect the logic levels
Faster switching speeds
reduced load capacitance due to lower input capacitance (Cin)
reduced load capacitance due to smaller output loading (Cout)
no Isc, so all the current provided by PDN goes into discharging CL
CL being lower also contributes to power savings

46. Properties of Dynamic Gates, con’t
Power dissipation should be better
consumes only dynamic power – no short circuit power consumption since the pull-up path is not on when evaluating
lower CL- both Cint (since there are fewer transistors connected to the drain output) and Cext (since there the output load is one per connected gate, not two)
by construction can have at most one transition per cycle – no glitching
But power dissipation can be significantly higher due to
higher transition probabilities
extra load on CLK
PDN starts to work as soon as the input signals exceed VTn, so set VM, VIH and VIL all equal to VTn
low noise margin (NML)
Needs a precharge clock

47. Dynamic 4 Input NAND Gate
VDD
Out
In1
In2
In3
In4 f
GND

48. Issues in Dynamic Design 1: Charge Leakage
CLK
Clk Mp
Out CL A
leakage sources are reverse-biased diode and the sub-threshold leakage of the NMOS pulldown device.
Charge stored on CL will leak away with time (input in low state during evaluation)
Requires a minimum clock rate - so not good for low performance products such as watches (or when have conditional clocks)
PMOS precharge device also contributes some leakage due to reverse bias diode and subthreshold conduction that, to some extent, offsets the leakage due to the pull down paths.
Evaluate
VOut
Clk Me
Precharge
Leakage sources
Dominant component is subthreshold current

49. Impact of Charge Leakage
Output settles to an intermediate voltage determined by a resistive divider of the pull-up and pull-down networks
Once the output drops below the switching threshold of the fan-out logic gate, the output is interpreted as a low voltage.
CLK
Out

50. A Solution to Charge Leakage
Keeper compensates for the charge lost due to the pull- down leakage paths.
Keeper
CLK Mp
Mkp
!Out CL A
During precharge, Out is VDD and inverter out is GND, so keeper is on
During evaluation if PDN is off, the keeper compensates for drained charge due to leakage.
If PDN is on, there is a fight between the PDN and the PUN - circuit is ratioed so PDN wins, eventually
Note Psc during switching period when PDN and keeper are both on simultaneously B
CLK Me
Same approach as level restorer for pass transistor logic

51. Issues in Dynamic Design 2: Charge Sharing
Charge stored originally on CL is redistributed (shared) over CL and CA leading to static power consumption by downstream gates and possible circuit malfunction.
CLK Mp
Out CL A Ca
B=0
CA initially discharged and CL fully charged. Cb
CLK Me
When Vout = - VDD (Ca / (Ca + CL )) the drop in Vout is large enough to be below the switching threshold of the gate it drives causing a malfunction.

52. Charge Sharing Example
What is the worst case voltage drop on y? (Assume all inputs are low during precharge and that all internal nodes are initially at 0V.)
Load
inverter
CLK
y = A  B  C
Cy=50fF A !A a
Ca=15fF b B
Cb=15fF !B B !B
For class handout c d
Cc=15fF
Cd=10fF !C C
CLK

53. Charge Sharing Example
What is the worst case voltage drop on y? (Assume all inputs are low during precharge and that all internal nodes are initially at 0V.)
Cy=50fF
CLK A !A B !B C !C
y = A  B  C
Ca=15fF
Cc=15fF
Cb=15fF
Cd=10fF
Load
inverter a b d c
For lecture – should work up a different example than the one in the book (like just set the internal capacitances different)
Output stays high for 4 out of 8 cases (!A B C, !A !B !C, A !B C, and A B !C)
Worst case is obtained by exposing the maximum amount of internal capacitance to the output node during evaluation. This happens when !A B C or A !B C
30/(30+50) * 2.5 V = V so the output drops to = 1.56 V which is below the switching threshold of the Load inverter.
Vout = - VDD ((Ca + Cc)/((Ca + Cc) + Cy))
= - 2.5V*(30/(30+50)) = -0.94V, so the output drops to = V

54. Solution to Charge Redistribution
Clk
Clk Mp
Mkp
Out A B
Clk Me
Precharge internal nodes using a clock-driven transistor (at the cost of increased area and power)

55. Issues in Dynamic Design 4: Clock Feedthrough
Coupling between Out and Clk input of the precharge device due to the gate to drain capacitance. So voltage of Out can rise above VDD. The fast rising (and falling edges) of the clock couple to Out.
Clk Mp
Out CL A
Danger is that signal levels can rise enough above VDD that the normally reverse-biased junction diodes become forward-biased causing electrons to be injected into the substrate. B
Clk Me
The danger of the clock feedthrough is that it may cause the normally reverse bias
junction diodes of the precharged transistor to become forward bias.

56. Clock Feedthrough Clock feedthrough Clk Out In1 In2 In3 In & Clk In4
Voltage
In4
Out
Clk
Time, ns
Clock feedthrough

57. Clock Feedthrough and Charge Sharing
Out without charge redistribution (Ma off) 1 2 3 4 6 V ( o l t ) f
internal node X in PDN
feedthrough
out with charge redistribution effects (Ma on) t
(nsec)

58. Cascading Dynamic Gates issuesV
Clk
Clk
Clk Mp Mp
Out2
Out1 In In
Out1
Out2 should remain at VDD since Out1 transitions to 0 during evaluation. However, since there is a finite propagation delay for the input to discharge Out1 to GND, the second output also starts to discharge.
The second dynamic inverter turns off (PDN) when Out1 reaches VTn.
Setting all inputs of the second gate to 0 during precharge will fix it.
Correct operation is guaranteed (ignoring charge redistribution and leakage) as long as the inputs can only make a single 0 -> 1 transition during the evaluation period
VTn
Clk
Clk Me Me
Out2 V
Out2 should remain at VDD since Out1 transitions to 0 during evaluation. However, since there is a finite propagation delay for the input to discharge Out1 to GND, the second output also starts to discharge. t
Only one stage at a time should make a 1 to 0 transition!
The second dynamic inverter turns off (PDN) when Out1 reaches VTn.
Only 0  1 transitions allowed at inputs!

59. Domino Logic: High performance dynamic CMOS circuits
CLK Mp
Mkp
CLK Mp
Out1
Out2
1  1
1  0
0  0
0  1
In1
In4
PDN
In2
PDN
Ensures all inputs to the Domino gate are set to 0 at the end of the precharge period. Hence, the only possible transition during evaluation is 0 -> 1
Additional advantage is that the fan-out of the gate is driven by a static inverter with a low-impedance output that increases the noise immunity.
The buffer also reduces the capacitance of the dynamic output node by separating internal and load capacitances.
Finally, the inverter can be used to drive a bleeder to combat leakage and charge redistribution.
In5
In3
CLK Me
CLK Me
Ensures all inputs to the Domino gate are set to 0 at the end of the precharge period. Hence, the only possible transition during evaluation is 0 -> 1
Additional advantage is that the fan-out of the gate is driven by a static inverter with a low-impedance output that increases the noise immunity.
The buffer also reduces the capacitance of the dynamic output node by separating internal and load capacitances

60. Domino Logic
Solves problem of cascading dynamic gates, but is non- inverting
Add an inverter between dynamic gates
Inverter drives the gate’s fanout – increased performance
Sometimes the inverter is replaced with a more complex static CMOS gate
Static CMOS gate improves dynamic noise margins
Solve non-inverting problem by implementing both F and F separately
Area/power doubles

61. Why Domino? Like falling dominos! Ini PDN Inj Ini Inj PDN Ini PDN Inj
CLK
In1
CLK
During the precharge phase all input will be turned off because all buffer output are 0.
During the evaluation phase, each buffer output at most can make one transition from 0 to 1.
Like falling dominos!