Presentation is loading. Please wait.

Presentation is loading. Please wait.

Lecture #8 Page 1 Lecture #8 Agenda 1.VHDL : Operators 2.VHDL : Signal Assignments Announcements 1.HW #4 assigned ECE 4110– Sequential Logic Design.

Published byNathaniel Armstrong Modified over 8 years ago

Similar presentations

Presentation on theme: "Lecture #8 Page 1 Lecture #8 Agenda 1.VHDL : Operators 2.VHDL : Signal Assignments Announcements 1.HW #4 assigned ECE 4110– Sequential Logic Design."— Presentation transcript:

1 Lecture #8 Page 1 Lecture #8 Agenda 1.VHDL : Operators 2.VHDL : Signal Assignments Announcements 1.HW #4 assigned ECE 4110– Sequential Logic Design

2 Lecture #8 Page 2 VHDL Operators VHDL Operators - Data types define both "values" and "operators" - There are "Pre-Determined" data types Pre-determined = Built-In = STANDARD Package - We can add additional types/operators by including other Packages - We'll first start with the STANDARD Package that comes with VHDL

3 Lecture #8 Page 3 VHDL Operators Logical Operators - works on types BIT, BIT_VECTOR, BOOLEAN - vectors must be same length - the result is always the same type as the input not and nand or nor xor xnor

4 Lecture #8 Page 4 VHDL Operators Numerical Operators - works on types INTEGER, REAL - the types of the input operands must be the same +"addition" - "subtraction" * "multiplication" / "division" mod "modulus" rem "remainder" abs "absolute value" ** "exponential" ex) Can we make an adder circuit yet? A,B: inBIT_VECTOR (7 downto 0) Z : out BIT_VECTOR (7 downto 0) Z <= A + B;

5 Lecture #8 Page 5 VHDL Operators Relational Operators - used to compare objects - objects must be of same type - Output is always BOOLEAN (TRUE, FALSE) - works on types: BOOLEAN, BIT, BIT_VECTOR, CHARACTER, INTEGER, REAL, TIME, STRING ="equal" /= "not equal" "greater than" >= "greater than or equal"

6 Lecture #8 Page 6 VHDL Operators Shift Operators - works on one-dimensional arrays - works on arrays that contain types BIT, BOOLEAN - the operator requires 1) An Operand (what is to be shifted) 2) Number of Shifts (specified as an INTEGER) - a negative Number of Shifts (i.e., "-") is valid and reverses the direction of the shift sll"shift left logical" srl "shift right logical" sla "shift left arithmetic" sra "shift right arithmetic" rol "rotate left" ror "rotate right"

7 Lecture #8 Page 7 VHDL Operators Concatenation Operator - combines objects of same type into an array - the order is preserved & "concatenate" ex) New_Bus <= ( Bus1(7:4) & Bus2(3:0) )

8 Lecture #8 Page 8 VHDL Operators STD_LOGIC_1164 Operators - To expand the data types we have in VHDL, we include the IEEE Package "STD_LOGIC_1164" - This gives us the data types: STD_LOGIC STD_LOGIC_VECTOR - This gives us all of the necessary operators for these types Logical Numerical Relational Shift

9 Lecture #8 Page 9 VHDL Operators Assignment Operators - The assignment operator is <= - The Results is always on the Left, Operands on the Right - Types need to all be of the same type - need to watch the length of arrays! Ex)x <=y; a <= b or c; sum <= x + y; NewBus <= m & k;

10 Lecture #8 Page 10 Delayed Assignments Delay Modeling - VHDL allows us to include timing information into assignment statements - this gives us the ability to model real world gate delay - we use the keyword "after" in our assignment followed by a time operand. Ex) B <= not A after 2ns; - VHDL has two types of timing models that allow more accurate representation of real gates 1) Inertial Delay (default) 2) Transport Delay

11 Lecture #8 Page 11 Delayed Assignments Inertial Delay - if the input has two edge transitions in less time than the inertial delay, the pulse is ignored said another way… - if the input pulse width is smaller than the delay, it is ignored - this models the behavior of trying to charge up the gate capacitance of a MOSFET ex) B <= A after 5ns; any pulses less than 5ns in width are ignored.

12 Lecture #8 Page 12 Delayed Assignments Transport Delay - transport delay will always pass the pulse, no matter how small it is. - this models the behavior of transmission lines - we have to explicitly call out this type of delay using the "transport" keyword ex) B <= transport A after 5ns; B <= transport not A after t_delay; -- here we used a constant

Download ppt "Lecture #8 Page 1 Lecture #8 Agenda 1.VHDL : Operators 2.VHDL : Signal Assignments Announcements 1.HW #4 assigned ECE 4110– Sequential Logic Design."

Similar presentations

INTRO TO VHDL Appendix A: page 779 - page 831 1. VHDL is an IEEE and ANSI standard. VHDL stands for Very High Speed IC hardware description language.

INTRO TO VHDL Appendix A: page page VHDL is an IEEE and ANSI standard. VHDL stands for Very High Speed IC hardware description language.
Table 7.1 Verilog Operators.

Table 7.1 Verilog Operators.
1 Lecture 13 VHDL 3/16/09. 2 VHDL VHDL is a hardware description language. The behavior of a digital system can be described (specified) by writing a.

1 Lecture 13 VHDL 3/16/09. 2 VHDL VHDL is a hardware description language. The behavior of a digital system can be described (specified) by writing a.
EE 261 – Introduction to Logic Circuits Module #5 Page 1 EE 261 – Introduction to Logic Circuits Module #5 - VHDL Topics A.Hardware Description Languages.

EE 261 – Introduction to Logic Circuits Module #5 Page 1 EE 261 – Introduction to Logic Circuits Module #5 - VHDL Topics A.Hardware Description Languages.
VHDL ELEC 418 Advanced Digital Systems Dr. Ron Hayne Images Courtesy of Thomson Engineering.

VHDL ELEC 418 Advanced Digital Systems Dr. Ron Hayne Images Courtesy of Thomson Engineering.
VHDL 3 BASIC OPERATORS AND ARCHITECTURE BODY Design descriptions & Design constructions examples are taken from foundation series examples exercise 3:

VHDL 3 BASIC OPERATORS AND ARCHITECTURE BODY Design descriptions & Design constructions examples are taken from foundation series examples exercise 3:
Introduction to VHDL (Lecture #5) ECE 331 – Digital System Design The slides included herein were taken from the materials accompanying Fundamentals of.

Introduction to VHDL (Lecture #5) ECE 331 – Digital System Design The slides included herein were taken from the materials accompanying Fundamentals of.
Comprehensive VHDL Module 6 Types November 2000. 6-2 Comprehensive VHDL: Types Copyright © 2000 Doulos Types Aim ©To understand the use and synthesis.

Comprehensive VHDL Module 6 Types November Comprehensive VHDL: Types Copyright © 2000 Doulos Types Aim ©To understand the use and synthesis.
VHDL Data Types Module F3.1. VHDL Data Types Scalar Integer Enumerated Real (floating point)* Physical* Composite Array Record Access (pointers)* * Not.

VHDL Data Types Module F3.1. VHDL Data Types Scalar Integer Enumerated Real (floating point)* Physical* Composite Array Record Access (pointers)* * Not.
Data Types. Composite Date Types n Arrays –Single and multi-dimensional –Arrays are single Type n Records –Records are mixed types.

Data Types. Composite Date Types n Arrays –Single and multi-dimensional –Arrays are single Type n Records –Records are mixed types.
CS 3850 Lecture 5 Operators. 5.1 Binary Arithmetic Operators Binary arithmetic operators operate on two operands. Register and net (wire) operands are.

CS 3850 Lecture 5 Operators. 5.1 Binary Arithmetic Operators Binary arithmetic operators operate on two operands. Register and net (wire) operands are.
VHDL. What is VHDL? VHDL: VHSIC Hardware Description Language  VHSIC: Very High Speed Integrated Circuit 7/2/2015 2 R.H.Khade.

VHDL. What is VHDL? VHDL: VHSIC Hardware Description Language  VHSIC: Very High Speed Integrated Circuit 7/2/ R.H.Khade.
1 Part II: VHDL CODING. 2 Design StructureData TypesOperators and AttributesConcurrent DesignSequential DesignSignals and VariablesState Machines A VHDL.

1 Part II: VHDL CODING. 2 Design StructureData TypesOperators and AttributesConcurrent DesignSequential DesignSignals and VariablesState Machines A VHDL.
EELE 367 – Logic Design Module 3 – VHDL Agenda

EELE 367 – Logic Design Module 3 – VHDL Agenda
Lecture #6 Page 1 Lecture #6 Agenda 1.VHDL - Architecture 2.VHDL - Packages Announcements 1.HW #3 assigned ECE 4110– Sequential Logic Design.

Lecture #6 Page 1 Lecture #6 Agenda 1.VHDL - Architecture 2.VHDL - Packages Announcements 1.HW #3 assigned ECE 4110– Sequential Logic Design.
Chapter 6. Dataflow Modeling. Continuous Assignments The left hand side always be a scalar or vector net or a concatenation of scalar and vector nets.

Chapter 6. Dataflow Modeling. Continuous Assignments The left hand side always be a scalar or vector net or a concatenation of scalar and vector nets.
Programmable Logic Architecture Verilog HDL FPGA Design Jason Tseng Week 5.

Programmable Logic Architecture Verilog HDL FPGA Design Jason Tseng Week 5.
Digital Arithmetic and Arithmetic Circuits

Digital Arithmetic and Arithmetic Circuits
A VHDL Tutorial ENG2410. ENG241/VHDL Tutorial2 Goals Introduce the students to the following: –VHDL as Hardware description language. –How to describe.

A VHDL Tutorial ENG2410. ENG241/VHDL Tutorial2 Goals Introduce the students to the following: –VHDL as Hardware description language. –How to describe.
IAY 0600 Digital Systems Design

IAY 0600 Digital Systems Design

Similar presentations

Ads by Google