0. DESIGN RULES FOR HDI BOARD
Unimicron
Unimicron Technology Corp.
DESIGN RULES FOR HDI BOARD
REV.D DATE :
JOHNNY HSU徐 振 連

1. TYPE 1 HDI Boards Design Rulec k e d g f n l i h p m z
m-1
e-1
d-1
= Copper
= Prepreg
= Core
= Non-reinforced epoxy resin
Structure : 1+ x +1 , without IVH
where x is built as core substrate

2. TYPE 1 HDI Boards Design Rule (cont.)

3. TYPE 2 HDI Boards Design Rulek f g h e d n l z p o
e-1
d-1 i
m-1 c a b m j
= Copper
= Prepreg
= Core
= Non-reinforced epoxy resin
Structure : 1+ x +1 , with IVH
where x is built as core substrate

4. TYPE 2 HDI Boards Design Rule (cont.)

5. TYPE 3 HDI Boards Design Rulek f g e d l z p
e-1
d-1 i h
m-1 c a b m c’ a’ b’
c”-1 c” a” b” j q
= Copper
= Prepreg
= Core
= Non-reinforced epoxy resin
Structure : 2+ x +2 , IVH is optional
where x is built as core substrate

6. TYPE 3 HDI Boards Design Rule (cont.)

7. Inner/Outerlayer Design Diagram
plane edge
board edge
NPTH a b h c f g i o
e,e-1
d,d-1 n s r
microvia
through hole
innerlayer

8. Surface Mount Design Diagram
gold
b-1 t x
land size
routed feature
Sn-Pb v t
land size w u

9. Staggered Via Design Diagramc q b

10. 2 Layers HDI Design D
drill S L H 2 1 P
R-C SR
D drill : min. finished hole size - fhs (plated thruhole) 8 mil
P drill : surface via land (fhs + annular ring x 2)* fhs + 10 mil

11. 2 Layers HDI Design Staggered Via P1up D1 R1 Svia-via R2 S P1down
Scen-cen
qedq-edg S
Staggered Via
Svia-via : Min. Edge-to-edge distance between vias : 9 mil
R2 : Min. Microvia annular ring size/ target land : 3 mil
R1 : Min. Microvia annular ring size/ capture land : 2.5 mil
Scen-cen : Min. center-to-center distance between vias (pitch) : 13 mil
qedq-edg : min. staggered via land length : 23 mil

12. 2 Layers HDI Design Staggered Via P1up D1 R1 Svia-via R2 P1down
Scen-cen
qedq-edg
Staggered Via
S via-via : Min. Edge-to-edge distance between vias : 3 mil
R2 : Min. Microvia annular ring size/ target land : 3 mil
R1 : Min. Microvia annular ring size/ capture land : 2.5 mil
S cen-cen : Min. center-to-center distance between vias (pitch) : 7 mil
q edq-edg : min. staggered via land length : 17 mil

13. 2 Layers HDI Design Stacked Via Skip Via D S P D P H(max.) 2up 2middle
2down D
2up
2middle
Stacked Via D 3 P
3down
3up S
H(max.)
Skip Via

14. 2 Layers HDI Design (cont.)

15. 2 Layers HDI Design (cont.)

16. HDI Board Capability (Laser Buried & Blind Via)
Laser Via PCB Capability
Mass Production
Sample Run
Feature
(Normal)
Lower cost)
(High Vol.
Normal cost)
(High Vol.
Higher cost)
(Small Vol.)
Line /Spacing Width (Tra. Layers)
0.005 “/0.005”
0.004 “/0.004”
“/0.0035”
0.003 “/0.003”
Line /Spacing Width (HDI Layers)
0.005 “/0.005”
0.004 “/0.004”
0.003 “/0.003”
“/0.0025”
Drill Via Diameter (PTH)
0.010 “
0.010 “
0.010 “
0.008 “
Drill Capture Pad (PTH)
0.022 “
0.020 “
0.018 “
0.016 “
Microvia Diameter (Unfinished)
0.004 “
0.004 “
0.004 “
0.003 “
RCC
Microvia Capture Pad
0.014 “
0.012 “
0.011 “
0.009 “
Microvia Diameter (Unfinished)
Microvia Capture Pad
0.005 “
0.011 “
0.004 “
0.010 “
0.014 “
0.012 “ PP
Aspect Ratio (PTH)
8 : 1
9 : 1
10 : 1
11 : 1
Aspect Ratio (MicroVia)
0.6 : 1
0.8 : 1
0.9 : 1
1 : 1
Layer to Layer Reg. Tolerance
± 5 mil
± 4 mil
± 3 mil
± 2 mil
Impedance control tolerance
± 10%(± 5)
± 10%(± 4)
± 7 % (± 3)
± 5%(± 2.5)

17. Copper thickness vs. Line width5 10 15 20 25 30 35 40
100/100
75/75
50/50
25/25
L/S μ m
Pattern Pitch (μ m)
Allowable Thickness (um)
Resist L/S= 30/10um
Top=10um, K=1.6
Resist L/S= 45/15um
Top=20um, K=1.7
Resist L/S= 70/30um
Top=35um, K=1.8
Resist L/S= 100/50um
Top=60um, K=2.5
Resist L/S= 135/65um
Top=85um, K=2.7
Total Thickness (um)
Cu Foil(10um panel plating)
Cu Foil(15um panel plating)
Cu Foil(20um panel plating)
Courtesy of T.Yamamoto,T.Kataoka and J. Andresakis)
K :etch factor
Etch Factor =V/X