2. A combinational circuit is a connected arrangement of logic gate with a set of input and output.

3. Block diagram of a combinational circuits: M o/p variable N i/p variable Combinational circuit

4. A combinational circuit that performs the arithmetic addition of two bits is called a half adder.

5. Logic diagram: xycs 0000 0101 1001 1110 Truth table:

6. A combinational circuit that perform the arithmetical addition three bits is called full adder.

7. Logic diagram:::::FULL ADDER

8. xyzcS 00001 00101 01001 01110 10001 10110 11010 11111 Truth table ::::::FULL ADDER

9. The storage elements employed in clocked sequential circuit are called flip-flop. A flip flop is a binary cell capable of storing one bit of information. It has 2 output.one for the normal value,one for the compliment value of the bit stored in it.

10. The most common types of flip-flop are: 1.SR FLIP FLOP 2.D FLIP FLOP 3.JK FLIP FLOP 4.T FLIP FLOP

11. In the graphical signal it has three input.(s,r,c) It has an output “Q”and sometimes the flip- flop has a compliment output. There is an arrow shaped symbol in frond of the letter “C”to designate a dynamic input. The dynamic indicator symbol denote the fact that the flip-flop responds to a positive transition of the input clock signal.

12. S R C Q Q’ SRQ(t+1) 00Q(t),,,no change 010,,,clear to zero 101,,,set to one 11Indenter mined Characteristic table: Graphical symbol:

13. It is a slight modification of SR flip- flop. This converted to a D flip-flop by inserting an inverter b/n S and R and assigning the symbol D to the single input.

14. It is a slight modification of a SR flip flop. D C Q Q’ DQ(t+1) 00,,,clear to zero 11,,,set to 1 Characteristic table: Graphical symbol:

15. A JK flip-flop is a refinement of the SR flip-flop in that the determined condition of the SR type is defined in the JK type. Input J and K behaves like input S and R to set and clear the flip-flop,respectively.

16. J K C Q Q’ JKQ(t+1) 00Q(t),,,no change 010,,,clear to 0 101,,,set to 1 11Q’(t),,, compliment

17. TQ C Q’ TQ(t+1) 0Q(t),,,no change 1Q’(t),,,complement

18. The most common type of flip-flop used to synchronize the state change during a clock pulse transition is the edge triggered flip- flop. In this, output transition occur at a specific level of the clock pulse.

19. C D Q CLOCK Positive clock transition

20. D C Q Negative clock transition

21. A decoder is a combinational circuit that convert binary information from the n coder input to a maximum of 2n unique output. If the n bit coder information has unused bit combination,the decoder may have less than 2n output.

23. EA2A1A0D7D6D5D4D3D2D1D0 0***00000000 100000000001 100100000010 101000000100 101100001000 110000010000 110000100000 111001000000 111110000000 TRUTH RABLE FOR 3-8 LINE DECODER

25. An encoder is a digital circuit that performs the inverse operation of a decoder. An encoder has 2n input lines and n output lines and n output lines. The encoder can be implemented with OR gate whose input are determined from the truth table.

26. D0 D1 D2 D3 A0 A1 I/P O/P

27. A sequential circuit is an interconnection of flip-flop and gate. Combinational circuit Flip-flop clock input output

28. Example of sequential circuit:

30. State diagram: