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Combinational Logic: Other Gate Types
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Gate classifications Primitive gate - a gate that can be described using a single primitive operation type (AND or OR) plus an optional inversion(s). Complex gate - a gate that requires more than one primitive operation type for its description
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Fall 2005 primitive gates NAND NOR
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NAND Gates
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NOR NOT OR Also common
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NAND is Universal Universal gate : Can express any Boolean Function using only this type of gate Equivalents below
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Sum of Products with NAND
Easy to think of bubbles as canceling
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AND-OR Circuit Easy to Convert
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NOR Also Universal Dual of NAND
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Buffer No inversion No change, except in power or voltage
Used to enable driving more inputs
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Parity Function How does parity work ?
Fall 2005 Parity Function How does parity work ? Given 7- bit ASCII code for A ( ) What is the ASCII code for A with even parity ? Write truth table for two input even parity generator What needs to be generated for parity bit? What function of two inputs gives you this? This is called: Exclusive OR function In Chapter 1, a parity bit added to n-bit code to produce an n + 1 bit code Even parity – set bit to make number of 1’s even Examples A ( ) with even parity is C ( ) with even parity is X Y P 0 0 0 0 1 1 1 0 1 1 1 0 Exclusive OR
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Example Complex Digital Logic Gates: Exclusive OR/ Exclusive NOR
Fall 2005 Example Complex Digital Logic Gates: Exclusive OR/ Exclusive NOR The Exclusive OR (XOR) function is defined as: The eXclusive NOR (XNOR) function, otherwise known as equivalence is: Y X + = Å Y X + = Å
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Symbols For XOR and XNOR
XOR symbol: XNOR symbol: Symbols exist only for two inputs
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Truth Tables for XOR/XNOR
Fall 2005 Operator Rules: XOR XNOR The XOR function means: X OR Y, but NOT BOTH Why is the XNOR function also known as the equivalence function, denoted by the operator ? X Y Å 1 X Y 1 or X (X Å Y) Because it is defined as X Y + X’ Y’ that equals 1 if and only if X = Y implying X is equivalent to Y.
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XOR Implementations The simple SOP implementation uses the following structure: A NAND only implementation is: X Y X + = Å X Y Y X X Y Y
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XOR/XNOR (Continued) Z Y X Å Å = + + + = Y Z ) ( X 1 Å = =
Fall 2005 The XOR function can be extended to 3 or more variables. For more than 2 variables, it is called an odd function or modulo 2 sum (Mod 2 sum), not an XOR: The complement of the odd function is the even function. The XOR identities: Z Y X Å Å = + + + X 1 Å = Y Z ) ( = = For an odd function to be 1, with three or more variables an odd number of variables must be = to 1
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Question Draw the K-map of a 4 variable odd function 1 B C D A
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Example: Odd Function Implementation
Design a 3-input odd function F = X Y Z with 2-input XOR gates +
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Example: Odd Function Implementation
Design a 3-input odd function F = X Y Z with 2-input XOR gates Factoring, F = (X Y) Z + +
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Example: Odd Function Implementation
Design a 3-input odd function F = X Y Z with 2-input XOR gates Factoring, F = (X Y) Z The circuit: + + X Y Z F
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Example: Odd Function Implementation
Design a 3-input odd function F = X Y Z with 2-input XOR gates Factoring, F = (X Y) Z The circuit: Based on the above, given (X,Y,Z,F), then F would be the even parity bit for the three bits X,Y,Z. Hence, the circuit is an even parity generator. + + X Y Z F
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Even Parity Generators and Checkers
An even parity bit could be added to n-bit code to produce an n + 1 bit code: Use an odd function to produce codes with even parity Use odd function circuit to check code words with even parity Example: n = 3. Generate even parity code words of length 4 with an odd function circuit (parity generator): Check even parity code words of length 4 with odd function circuit Operation: (X,Y,Z) = (0,0,1) gives (X,Y,Z,P) = (0,0,1,1) and E = 0. If Y changes from 0 to 1 between generator and checker, then E = 1 indicates an error. X Y Z P E
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Odd Parity Generators and Checkers
Similarly, an odd parity bit could be added to n-bit code to produce an n + 1 bit code Use an even function to produce codes with odd parity Use even function circuit to check code words with odd parity
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Tri-State Output w/ 3 states: H, L, and Hi-Z High impedance
Behaves like no output connection if in Hi-Z (Hi Impedance) state Allows connecting multiple outputs
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Data Selection If s = 0, OL = IN0, else OL = IN1 IN0 OL IN1 s
Data Selector (2 to 1 Multiplexer) IN0 IN1 OL s
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Data Selection Function Implementation with 3-State Logic
Data Selection Function: If s = 0, OL = IN0, else OL = IN1 Performing data selection with 3-state buffers: Since EN0 = S and EN1 = S, one of the two buffer outputs is always Hi-Z plus the last row of the table never occurs. EN0 IN0 EN1 IN1 OL X 1 IN0 IN1 EN0 EN1 S OL
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