1. CSCI-365 Computer Organization Lecture Note: Some slides and/or pictures in the following are adapted from: Computer Organization and Design, Patterson & Hennessy, ©2005 Some slides and/or pictures in the following are adapted from: slides ©2008 UCB Chapter 4

2. Truth Tables Uniquely Define CL Function

3. Truth Table A truth table defines the outputs of a logic block for each set of inputs –E.g., Consider a block with 3 inputs A, B, C and an output E that is true only if exactly 2 inputs are true (DONE IN CLASS)

4. Logic Gates

6. 2-input gates extend to n-inputs N-input XOR is the only one which isn’t so obvious It’s simple: XOR is a 1 iff the # of 1s at its input is odd 

7. Boolean Algebra George Boole, 19 th Century mathematician Developed a mathematical system (algebra) involving logic –later known as “Boolean Algebra” Primitive functions: AND, OR and NOT The power of BA is there’s a one-to-one correspondence between circuits made up of AND, OR and NOT gates and equations in BA + means OR, means AND, x means NOT

8. Canonical Forms Sum of products

9. Laws of Boolean Algebra

10. BA: Circuit & Algebraic Simplification BA also great for circuit verification Circ X = Circ Y? use BA to prove!

11. Canonical Forms

12. Truth Table  Gates (e.g., majority circ.) (DONE IN CLASS)

13. Common Logic Blocks - Multiplexor Multiplexor or selector: one of N inputs is reflected on the output depending on the value of the log 2 N selector bits. E.g., 2-input mux

14. Takes in N inputs and activates one of 2 N outputs I 0 I 1 O 0 O 1 O 2 O 3 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 0 0 0 1 2-to-4 Decoder I0I0 O0O0 Common Logic Blocks - Decoder I1I1 O1O1 O2O2 O3O3 2-4 Decoder (DONE IN CLASS)

15. Arithmetic and Logic Unit Most processors contain a special logic block called “Arithmetic and Logic Unit” (ALU)

16. Arithmetic and Logic Unit A common way to implement the ALU is to provide a CL block for each of the possible ALU functions –The inputs, A and B, get distributed to all the blocks –The output of the proper block is selected with a mux –Every function of the ALU is computed internally to the ALU on every cycle, but only one of the results is sent to the output

17. Arithmetic and Logic Unit The logical operations as defined by the MIPS ISA are bitwise operations –In the case of AND, the resultant bit r i is generated as a i AND b i. The circuit to perform this operation is simply a collection of 32 AND gates –Similarly, the OR block is a collection of 32 OR gates The add/subtract block is significantly more complex

18. Adder/Subtracter Design -- how? Truth-table, then determine canonical form, then minimize and implement as we’ve seen before –This technique is only effective for very narrow adders, truth table too large for wider adders Look at breaking the problem down into smaller pieces that we can cascade or hierarchically layer –We will design the smaller pieces individually, then wire them together to create entire wide adder

19. 1-Bit Adder (DONE IN CLASS)

20. Multiplexor selects between ADD, OR, AND operations 1-Bit ALU with ADD, OR, AND

21. 1-bit ALUs are connected “in series” with the carry-out of 1 box going into the carry-in of the next box 32-Bit Ripple Carry Adder

22. Must invert bits of B and add a 1 Include an inverter CarryIn for the first bit is 1 The CarryIn signal (for the first bit) can be the same as the Binvert signal Incorporating Subtraction

23. Incorporating NOR

24. Perform a – b and check the sign New signal (Less) that is zero for ALU boxes 1-31 The 31 st box has a unit to detect overflow and sign – the sign bit serves as the Less signal for the 0 th box Incorporating SLT

25. Perform a – b and confirm that the result is all zero’s Incorporating BEQ

27. ALU §4.4 A Simple Implementation Scheme ALU controlFunction 0000AND 0001OR 0010add 0110subtract 0111set-on-less-than 1100NOR

28. What about overflow? Highest adder –C in, but no C out  A,B both > 0, overflow! –C out, but no C in  A,B both < 0, overflow! –C in, C out  no overflow! –no C in, no C out  no overflow! What op?

29. What are the values of the control lines and what operations do they correspond to?

30. Speed of Ripple Carry The carry propagates through every 1-bit box: each 1-bit box sequentially implements AND and OR – total delay is the time to go through 64 gates!

31. Faster Addition: Carry Lookahead Key to speeding up addition is determining the carry into the high-order bits sooner –We’ve already seen that any logic equation can be expressed as the sum of products – so it should be possible to compute the result by going through only 2 gates! (IN CLASS)

32. Faster Addition: Carry Lookahead Caveat: need many parallel gates and each gate may have a very large number of inputs – it is difficult to efficiently build such large gates, so we find a compromise: – moderate number of gates – moderate number of inputs to each gate – moderate number of sequential gates traversed

33. Processor Computer Control Datapath Memory (passive) (where programs, data live when running) Devices Input Output Keyboard, Mouse Display, Printer Disk (where programs, data live when not running) Five Components of a Computer

34. Processor (CPU): the active part of the computer, which does all the work (data manipulation and decision-making) –Datapath: portion of the processor which contains hardware necessary to perform operations required by the processor (the brawn) –Control: portion of the processor (also in hardware) which tells the datapath what needs to be done (the brain) The CPU

35. Our implementation of the MIPS is simplified –memory-reference instructions: lw, sw –arithmetic-logical instructions: add, sub, and, or, slt –control flow instructions: beq, j Generic implementation –use the program counter (PC) to supply the instruction address and fetch the instruction from memory (and update the PC) –decode the instruction (and read registers) –execute the instruction All instructions (except j ) use the ALU after reading the registers Fetch PC = PC+4 DecodeExec

36. Fetching Instructions Fetching instructions involves –reading the instruction from the Instruction Memory –updating the PC to hold the address of the next instruction –PC is updated every cycle, so it does not need an explicit write control signal –Instruction Memory is read every cycle, so it doesn’t need an explicit read control signal Read Address Instruction Memory Add PC 4

37. Decoding Instructions Decoding instructions involves –sending the fetched instruction’s opcode and function field bits to the control unit –reading two values from the Register File Register File addresses are contained in the instruction Instruction Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 Control Unit

38. Executing R Format Operations R format operations ( add,sub,slt,and,or ) –perform the (op and funct) operation on values in rs and rt –store the result back into the Register File (into location rd) –The Register File is not written every cycle (e.g. sw ), so we need an explicit write control signal for the Register File R-type: 3125201550 oprsrtrdfunctshamt 10 Instruction Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU overflow zero ALU controlRegWrite

39. Executing Load and Store Operations Load and store operations involve –compute memory address by adding the base register (read from the Register File during decode) to the 16-bit signed-extended offset field in the instruction –store value (read from the Register File during decode) written to the Data Memory –load value, read from the Data Memory, written to the Register File Instruction Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU overflow zero ALU controlRegWrite Data Memory Address Write Data Read Data Sign Extend MemWrite MemRead 1632

40. Executing Branch Operations Branch operations involves –compare the operands read from the Register File during decode for equality ( zero ALU output) –compute the branch target address by adding the updated PC to the 16- bit signed-extended offset field in the instr Instruction Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU zero ALU control Sign Extend 1632 Shift left 2 Add 4 PC Branch target address (to branch control logic)

41. Executing Jump Operations Jump operation involves –replace the lower 28 bits of the PC with the lower 26 bits of the fetched instruction shifted left by 2 bits Read Address Instruction Memory Add PC 4 Shift left 2 Jump address 26 4 28

42. Creating a Single Datapath from the Parts Assemble the datapath segments and add control lines and multiplexors as needed Single cycle design – fetch, decode and execute each instructions in one clock cycle –no datapath resource can be used more than once per instruction, so some must be duplicated (e.g., separate Instruction Memory and Data Memory, several adders) –multiplexors needed at the input of shared elements with control lines to do the selection –write signals to control writing to the Register File and Data Memory Cycle time is determined by length of the longest path

43. ALU Control ALU used for –Load/Store: F = add –Branch: F = subtract –R-type: F depends on funct field ALU controlFunction 0000AND 0001OR 0010add 0110subtract 0111set-on-less-than 1100NOR

44. ALU Control Assume 2-bit ALUOp derived from opcode –Combinational logic derives ALU control opcodeALUOpOperationfunctALU functionALU control lw00load wordXXXXXXadd0010 sw00store wordXXXXXXadd0010 beq01branch equalXXXXXXsubtract0110 R-type10add100000add0010 subtract100010subtract0110 AND100100AND0000 OR100101OR0001 set-on-less-than101010set-on-less-than0111

45. The Main Control Unit Control signals derived from instruction 0rsrtrdshamtfunct 31:265:025:2120:1615:1110:6 35 or 43rsrtaddress 31:2625:2120:1615:0 4rsrtaddress 31:2625:2120:1615:0 R-type Load/ Store Branch opcodealways read read, except for load write for R-type and load sign-extend and add

46. Single Cycle Datapath with Control Unit Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch

47. Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch R-type Instruction Data/Control Flow

48. Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch Load Word Instruction Data/Control Flow Store Word Instruction?

49. Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch Branch Instruction Data/Control Flow

50. Jump Operation? Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch

51. Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch Shift left 2 0 1 Jump 32 Instr[25-0] 26 PC+4[31-28] 28 Adding the Jump Operation

52. Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch Shift left 2 0 1 Jump 32 Instr[25-0] 26 PC+4[31-28] 28 Can the Control Unit set all the control signals based solely on the opcode field of the instruction?

53. Single Cycle Disadvantages & Advantages Uses the clock cycle inefficiently – the clock cycle must be timed to accommodate the slowest instruction –especially problematic for more complex instructions like floating point multiply May be wasteful of area since some functional units (e.g., adders) must be duplicated since they can not be shared during a clock cycle but Is simple and easy to understand Clk lwswWaste Cycle 1Cycle 2

54. Where we are headed Single Cycle Problems: –what if we had a more complicated instruction like floating point? –wasteful of area One Solution: –use a “smaller” cycle time –have different instructions take different numbers of cycles –a “multicycle” datapath

55. Multicycle Datapath Break up the instructions into steps, each step takes a cycle Assume the clock cycle can accommodate at most one of the following operations –a memory access –a register file access (two reads or one write) –an ALU operation At the end of a cycle –store values for use in later cycles (easiest thing to do) –introduce additional “internal” registers

56. At the end of a cycle –Store values needed in a later cycle by the current instruction in an internal register (not visible to the programmer). All (except IR) hold data only between a pair of adjacent clock cycles (no write control signal needed) IR – Instruction RegisterMDR – Memory Data Register A, B – regfile read data registersALUout – ALU output register Multicycle Datapath Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout –Data used by subsequent instructions are stored in programmer visible registers (i.e., register file, PC, or memory)

57. Multicycle Datapath Several functional units are shared for different purposes –Need to add multiplexors –Need to expand existing multiplexors

58. The Multicycle Datapath with Control Signals Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

59. The Multicycle Datapath with Control Signals Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

60. Five Execution Steps Five execution steps –Instruction Fetch –Instruction Decode and Register Fetch –Execution, Memory Address Computation, or Branch Completion –Memory Access or R-type instruction completion –Write-back step Instructions take from 3-5 cycles

61. Step 1: Instruction Fetch Use PC to get instruction and put it in IR Increment PC by 4 and put result back in PC IR <= Memory[PC]; PC <= PC + 4; What is the advantage of updating the PC now?

62. Step 1 Control Signals Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

63. Step 2: Instruction Decode and Register Fetch We don’t know yet what the instruction is –Read registers rs and rt in case we need them –Compute the branch address in case the instruction is a branch A <= Reg[IR[25:21]]; B <= Reg[IR[20:16]]; ALUOut <= PC + (sign-extend(IR[15:0]) << 2); We aren't setting any control lines based on the instruction type (we are busy "decoding" it in our control logic)

64. Step 2 Control Signals Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

65. Step 3 (instruction dependent) ALU is performing one of three functions, based on instruction type –Memory Reference ALUOut <= A + sign-extend(IR[15:0]); –R-type ALUOut <= A op B; –Branch if (A==B) PC <= ALUOut; –Jump PC <= {PC[31:28], (IR[25:0],2’b00)};

66. Step 3 (Memory Reference) Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

67. Step 3 (R-type) Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

68. Step 3 (Branch) Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

69. Step 3 (Jump) Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

70. Step 4 (R-type or memory-access) Loads and stores access memory MDR <= Memory[ALUOut]; or Memory[ALUOut] <= B; R-type instructions finish Reg[IR[15:11]] <= ALUOut;

71. Step 4 (Loads access memory) Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

72. Step 4 (Stores access memory) Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

73. Step 4 (R-type instructions finish) Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

74. Reg[IR[20:16]] <= MDR; Which instruction needs this? Step 5 (write-back)

75. Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

76. Multicycle Control Unit Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28