1. 1 CSE 140L Discussion How to design your CPU (and how it works!)

2. CPU Design First read the specification and make sure you totally understand it. We only have 8 instructions. For today’s discussion, we will concentrate only on the first six. Looking at the ISA, we must first determine what our CPU requires. How many registers? (We need 3 registers) What operations (and hence modules) do we need in our ALU? (We have to support an adder and a multiplier) We can start designing both the ALU and register file now.

3. Datapath Our ALU will be pretty simple: Two data inputs, two modules, and one output, with a MUX that determines which one it is. Arithmetic Logic Unit ALU Out [3..0] Add Mul t ALU_Sel Data1 [3…0] Data2 [3…0]

4. Datapath The reg file is more complex: We need 3 registers, each with their own enable lines. We also need a MUX in front of R1 so that we can select what data to send to it (either from the move instruction or from R3 instruction). Register File ALU_Out R1Out [3..0] R2Out [3..0] R1 Inst [3..0] R1_en R2 R2_en R3 R3_en Reg_Clr R1_Sel Reg_Clr

5. Control Path Once we have that figured out, we need to examine the control lines required. Our ALU will only require one control line, ALU_Sel, to determine which operation to support. Our register file however will require more. The init instruction will be done via a “CLR” line into all our registers. Each register will have its own register enable line. And finally we will need to a control line to the multiplexer that determines the input into R1 (either from the move instruction, or from R3). We then need to figure out what the control unit should do for each instruction. This just requires us to go through each of the instructions, draw out the state table for each of the outputs, and figure out what each instruction should be doing.

6. Control Path We then need to figure out what the control unit should do for each instruction. This just requires us to go through each of the instructions, draw out the state table for each of the outputs, and figure out what each instruction should be doing. We can have don’t cares too. InstR1_enR2_enR3_enR1_SelReg_CLRALU_Sel 000111DC1 00110000DC

7. Control Path Once we have finished that table we can draw out the logic. In this lab, let’s design the control unit using VHDL instead of an ugly schematic. begin process(instr) begin if (instr(2 downto 0) = "000") then clr <= '1'; r1_sel <= '0'; r1_en <= '1'; r2_en <= '1'; r3_en <= '1'; comp_en <= '1'; pc_en <= '0'; res_sel <= '0'; end if; if (instr(2 downto 0) = "001") then clr <= '0'; r1_sel <= '0'; r1_en <= '1'; r2_en <= '0'; r3_en <= '0'; comp_en <= '0'; pc_en <= '0'; res_sel <= '1'; end if;

8. Control Path The end result will be a control path unit that will read in the first 3 bits of our instruction (the opcode) and will output the proper values for each of the control lines. Control Unit (Instruction Decoder) Instruction [6..4] R1_enR2_enR3_enR1_SelReg_ClrALU_Sel