1. 1

2. 2 Figure 10.1 Truth table and schematic diagram for a binary half-adder. 10.1 Simple Adders Half-adder

3. 3 Figure 10.2 Truth table and schematic diagram for a binary full adder. Full-adder

4. 4 Adders Half adder: add two digits without considering carry in.

5. 5 Full adder: add two digits and carry in.

6. 6 Figure 10.3 Full adder implemented with two half-adders, by means of two 4-input multiplexers, and as two-level gate network. xyCiCi CoCo S 00000 00101 01001 01110 10001 10110 11010 11111

7. 7 Figure 10.4 Ripple-carry binary adder with 32-bit inputs and output. Ripple-carry n-bit full-adder

8. 8 Figure 10.5 The main part of an adder is the carry network. The rest is just a set of gates to produce the g and p signals and the sum bits. Carry Propagation Networks

9. 9 Figure 10.6 The carry propagation network of a ripple-carry adder.

10. 10 Speed up of carry propagation: Provide a skip paths in a ripple-carry network. Carry equation remains the same for c 4j, c 4j+1, c 4j+2, c 4j+3, but c 4j+4 different.

11. 11 Figure 10.8 Driving analogy for carry propagation in adders with skip paths. Taking the freeway allows a driver who wants to travel a long distance to avoid excessive delays at many traffic lights.

12. 12 Figure 10.9 Schematic diagram of an initializable synchronous counter. 10.3 Counting and Incrementation Necessity: e.g., set a register to a value x, and repeatedly add a constant a. sequence values, x, x+1a, x+2a … Full adder + additional circuit

13. 13 Figure 10.10 Carry propagation network and sum logic for an incrementer. Incrementer: a =1 By setting cin=1, y=0, therefore,

14. 14 Brent-Kung carry lookahead network [a, b]: stands for (g [a,b], p [a,b] ) Carry operator : combines the generate and propagate signals for two adjacent block[i+1,j] and [h,i] of digital positions into respective signals for wider block [h,j]. 10.4 Design of Fast Adder

15. 15 G 01 = G 11 or ( P 11 and G 00 ) P01 = P 11 and P 00

16. 16 Figure 10.12 Brent-Kung lookahead carry network for an 8-digit adder, with only its top and bottom rows of carry operators shown. 8-input Brent-Kung network: composed of a 4-input Brent- kung network + two rows of carry operators.

17. 17 Blocks needed in the design of carry-lookahead adders with four-way grouping of bits.

18. 18 Figure 10.14 Carry-select addition principle. Carry-select adder K-bit adder: one (k/2)-bit adder in lower half + two (k/2)-bit adders in the upper half.

19. 19 16 bit Brent-Kung Carry Lookahead Network

20. 20 16 bit Sklansky adder

21. 21 Figure 10.15 Multiplexer-based logical shifting unit. 10.5 Logic and Shift Operations

22. 22 Figure 10.16 The two arithmetic shift instructions of MiniMIPS. Shift instruction in MiniMIPS: “shift right arithmetic ” and “shift right arithmetic variable” sra $t0, $s1, 2 # set $t0 to ($1) right-shifted by 2 srav $t0, $s1, $0# set $t0 to ($1) right-shifted by ($s0)

23. 23 Figure 10.17 Multistage shifting in a barrel shifter.

24. 24 Figure 10.18 A 4 × 8 block of a black-and-white image represented as a 32-bit word.

25. 25 10.6 Multifunction ALU ALU = adder + AND, OR, XOR, NOR gates Example in Fig.10.19 (1) Arithmetic operation: F 1 F 0 =10 –(i) add/Sub = 0: x+y –(ii) add/Sub = 1; x-y = x+y’+1 (2) Logic operation: F 1 F 0 =11, AND, OR, XOR, NOR (3) Shifter

26. 26 Figure 10.19 A multifunction ALU with 8 control signals (2 for function class, 1 arithmetic, 3 shift, 2 logic) specifying the operation.