1. Mehmet Can Vuran, Instructor University of Nebraska-Lincoln Acknowledgement: Schematics adapted from those provided by the authors Hennessey and Patterson.

2.  Common functions  AND  OR  NAND  NOR  Add  Sub 2

3.  Common functions  AND  OR  NAND  NOR  Add  Sub 3

4. 4 B A R Symbol: B A R B0B0 A0A0 R0R0 B1B1 A1A1 R1R1 B2B2 A2A2 R2R2 B3B3 A3A3 R3R3

5. 5 A: 1 0 0 1 B: 0 1 0 1 C: 0 0 0 1 0 1 1 1 0 A:A 3 A 2 A 1 A 0 B:B 3 B 2 B 1 B 0 C: S0S0 C1C1 S1S1 C2C2 S2S2 C3C3 S3S3 C4C4 Basic Building Block: Full Adder BiBi AiAi CiCi C i+1 SiSi AiAi BiBi CiCi SiSi 00000 00101 01001 01110 10001 10110 11010 11111 Truth Table: C0C0

6. 6 Full Adder B0B0 A0A0 C 0 =0 C1C1 S0S0 Full Adder B1B1 A1A1 C2C2 S1S1 Full Adder B2B2 A2A2 C3C3 S2S2 Full Adder B3B3 A3A3 C4C4 S3S3 A-B ? A:A 3 A 2 A 1 A 0 B:B 3 B 2 B 1 B 0 C: S0S0 C1C1 S1S1 C2C2 S2S2 C3C3 S3S3 C4C4 C0C0

7. 7 Full Adder B’ 0 A0A0 C 0 =1 C1C1 S0S0 Full Adder B’ 1 A1A1 C2C2 S1S1 Full Adder B’ 2 A2A2 C3C3 S2S2 Full Adder B’ 3 A3A3 C4C4 S3S3

8. 8 Full Adder A0A0 C1C1 S0S0 Full Adder B1B1 A1A1 C2C2 S1S1 Full Adder B2B2 A2A2 C3C3 S2S2 Full Adder B3B3 A3A3 C4C4 S3S3 B0B0 Add/Sub Function Select F: 0: Add 1: Sub Carry C Basic ALU AB S Symbol: Any other way? B-A ?

9. 9 00 01 10 MUX R G ALU B A R C F,G FG1G0R B A F C Basic ALU B A B A AND OR ADD/ SUB

10. 10 00 01 10 MUX R G ALU B A R C F,G FG1G0R -00And -01Or 010Add 110Sub -11- B A F C Basic ALU B A B A AND OR ADD/ SUB

11.  Carry (C): Already seen in the design of Adder/Subtractor  Overflow (V): Next slide  Sign (N): Just the sign bit  Zero (Z): Zero result 11 Exercise: Add logic to the ALU design to generate V, N and Z flags.

12.  Use the rule:  Carry-in to Sign-bit != Carry-out of Sign-bit 12 carry-in carry-out != Overflow What is the truth table? Exercise: Find the logic to implement overflow by other rules discussed earlier.

13.  Both A and B can be inverted before arithmetic and logical operations.  If Ainvert = Binvert = 1 and Operation = 00, we do:  A’ and B’ = A nor B  Similarly, Nand with Operation = 01.  Doing both A-B and B-A will require connecting Carryin via a mux. 13 Fig. B.5.9

14.  Quiz 3 – Chapter 3  Friday, Oct. 11 th (15 min)  Midterm – Chapter 1, 2, 3  Wednesday, Oct. 23 rd (50 min)  Quiz 4 – Chapter A  Monday, Oct. 28 th (15 min)  Test 2 – Chapters A & 5  Monday, Nov. 4 th (50 min) 14