1. SVT April 2006Alberto Annovi- IFAE 20061 SVT L’upgrade del Silicon Vertex Trigger (SVT) di CDF IFAE 2006 Alberto Annovi Istituto Nazionale di Fisica Nucleare Laboratori Nazionali di Frascati

2. SVT April 2006Alberto Annovi- IFAE 20062 Outline the Silicon Vertex Trigger (SVT) Motivations Working principles Performance Upgrade

3. SVT April 2006Alberto Annovi- IFAE 20063 Why and how? Trigger on B hadronic decays –B physics studies, eg. CP violation in B decays, Bs mixing –new particle searches, eg. Higgs, Supersymmetry A b-trigger is particularly important at hadron colliders –large B production cross section for B physics –high energy available to produce new particles decaying to b quarks –overwhelming QCD background O(10 3 ) need to improve S/B at trigger level Detect large impact parameter tracks from B decays using the fact that  (B)  1.5 ps secondary vertex primary vertex Technical challenge! ~ 1 mm

4. SVT April 2006Alberto Annovi- IFAE 20064 SVT: Input & Output Inputs: – L1 tracks from XFT ( , p T ) – digitized pulse heights from SVX II Functionalities: – hit cluster finding – pattern recognition – track fitting Outputs: – reconstructed tracks (d, , p T )

5. SVT April 2006Alberto Annovi- IFAE 20065 SVT Design Constraints Detector Raw Data Level 1 pipeline: 42 clock cycles Level 1 Trigger L1 Accept Level 2 Trigger Level 2 buffer: 4 events L2 Accept DAQ buffers L3 Farm Level 1 7.6 MHz Synchromous Pipeline 5.5  s Latency 30 kHz accept rate Level 2 Asynchromous 2 Stage Pipeline 20  s Latency 800 Hz accept rate Mass Storage (100 Hz) 7.6 MHz Crossing rate 30 kHz input rate O(10 3 ) SVX strips/event 2-D low-res COT tracks Latency O(20)  sec No Dead Time Resolution  offline SVT upgrade keep it fast @ high luminosity SVX read out after L1 At L3 it is too late SVT here

6. SVT April 2006Alberto Annovi- IFAE 20066 1.Find low resolution track candidates called “roads”. Solve most of the pattern recognition 2.Then fit tracks inside roads. Thanks to 1 st step it is much easier offline quality Super Bin (SB) Tracking in 2 steps

7. SVT April 2006Alberto Annovi- IFAE 20067 The Event... The Pattern Bank Pattern matching

8. SVT April 2006Alberto Annovi- IFAE 20068 Dedicated device: maximum parallelism Each pattern with private comparator Track search during detector readout AM: Associative Memory Bingo scorecard

9. SVT April 2006Alberto Annovi- IFAE 20069 New AM chip Parallel pattern recognition is performed by the Associative Memory an array of AMchips Pattern recognition happens during detector readout! Standard Cell UMC 0.18  m 10x10 mm die - 5000 patterns (was 128) 6 input hit buses (4Gbit/s) tested up to 40 MHz, simulated up to 50 MHz 3000 production chips on April 2005 good yield 70% Original AM chip

10. SVT April 2006Alberto Annovi- IFAE 200610 2nd step: Track Fitting Track confined to a thin pattern: fitting becomes easy Linear expansion in the hit positions x i : –Chi2 = Sum k ( (c ik x i )^2 ) –d = d 0 +a i x i ; phi = phi 0 + b i x i ; Pt =... Fit reduces to a few scalar products: fast evaluation –(DSP, FPGA …) Constants from detector geometry –Calculate in advance –Correction of mechanical alignments via linear algorithm fast and stable A tough problem made easy !

11. SVT April 2006Alberto Annovi- IFAE 200611 Constraint surface

12. SVT April 2006Alberto Annovi- IFAE 200612 SVT crates in CDF counting room

13. SVT April 2006Alberto Annovi- IFAE 200613 0 10 20 30 40 50 Latency (  s) Performance @ 10x10 31 20  s -500 -250 0 250 500 (  m) 35  m  33  m resol  beam   = 48  m 0.00 0.05 0.10 0.15 Impact parameter (cm) Efficiency Given a fiducial offline track with SVX hits in 4/4 layers used by SVT 0.8 SVT Impact parameter

14. SVT April 2006Alberto Annovi- IFAE 200614 d phi d Online beamline fit & correction Subtracted Raw x y  d = Y beam cos  – X beam sin 

15. SVT April 2006Alberto Annovi- IFAE 200615 Hadronic B decays with SVT L1: Two XFT tracks P t > 2 GeV; P t1 + P t2 > 5.5 GeV  < 135° L2: d 0 >100  m for both tracks Validation of L1 cuts with  >20° Lxy > 200  m d 0 (B)<140  m Two body decays @ 3 x 10 31 cm -2 s -1 SVT The SVT advantage: 3 orders of magnitude

16. SVT April 2006Alberto Annovi- IFAE 200616 Signal yield: ~2300 events S/B  6.5 (peak value) M hh (GeV) Ks D0 Hadron-hadron mass distribution See tomorrow talks for up to date B--> h h’ (M. Morello) and Bs mixing (Salamanna) SVT for hadronic Bs decays --> sesitivity at high  ms

17. SVT April 2006Alberto Annovi- IFAE 200617 SVT upgrade Speed up SVT execution –cope with high lumi –reduce dead-time --> increase LVL1 bandwidth --> physics output –extra features forward muon/electron trigger (Silicon only tracking) release SVT upper impact parameter cut beyond 1mm –(CDF note PUB/CDF7359 to be published as NIM) How to do that? –more powerful Associative Memory (32k --> 512k patterns) Improve pattern recognition resolution –Reduce number of roads to fit –Replace AMS, RW, HB, TF with Pulsar boards Support 512k pattern/wedge Higher clock frequency --> faster track fitting & I/O Deadtime  L2 processing time * L1 Accept rate

18. SVT April 2006Alberto Annovi- IFAE 200618 Tsukuba Chicago Fermilab Chicago Pisa 1 st Pulsar: Sequencer & Road Warrior Associative Memory 512k patterns 2 nd Pulsar: Hit Buffer 3 nd Pulsar: Track Fitter

19. SVT April 2006Alberto Annovi- IFAE 200619 24 AM++ installation 2 AM++ per 30 degrees 512k patterns pattern width 240  m was 600  m with 32kpatt. Currently using 512k patterns for maximum speed. Extend tracking applications: release upper I.p. cut Pt down to 1.5GeV RMS # fits 32k patt3242 128k patt2032 512k patt1218 Lumi = 100E30 cm -2 s -1

20. SVT April 2006Alberto Annovi- IFAE 200620 Pulsar in SVT++ Implement new boards with Pulsars: Fast enough to handle the new amount of data SVT interface built in Developers can concentrate on firmware (= board functionalities) The Pulsar board is a programmable board: 3 powerful FPGAs embedded RAM all CDF connectors modular mezzanines S-link I/O RAM extension Pulsar @ CDF --> FPGAs @ board devel. RAM mezzanine 4Mx48bits

21. SVT April 2006Alberto Annovi- IFAE 200621 The CDF’s Road Warrior RW: Remove ghosts majority logic: 4/5 SVX hits + XFT track better efficiency problem: duplicate roads (ghost) because of missing layers a common problem A clean solution for ghost removal: the road warrior board receives roads as they are found store them in a dedicated Associative Memory FPGA based each road is compared on-the-fly with previous roads AM algorithm: identify and drop duplicate roads O(10) clock cycles latency proceedings of 2004 IEEE (NSS / MIC), Rome, Italy, 16-22 Oct 2004

22. SVT April 2006Alberto Annovi- IFAE 200622 impact of L2 upgrades on L1 bandwidth Dead time % L1 accept rate (Hz) Before SVT Upgrade Lumi 20-50E30 Summer 2005 Lumi 90E30 18KHz 25KHz +7kHz (+40%) L1A bandwidth @ double inst. lumi. Lumi 45E30 full SVT upgrade lumi 150E30

23. SVT April 2006Alberto Annovi- IFAE 200623 SVT SLIM5 (LVL1) Fast Track (LVL2) Next challenge is silicon tracking at both Level 1 & Level 2 LHC, Super B factory What next ? IEEE Trans.Nucl.Sci. 51:391-400,2004

24. SVT April 2006Alberto Annovi- IFAE 200624 AMchip receives up to 6 parallel buses for 6 layers at frequency: AMchip now: 50 MHz (Level 2) Next generation: 100 MHz or more Goal: use SAME CHIP for Level 2 & 1 SLIM5: Tracking (detector + TDAQ) R&D for SuperB but TDAQ could be OK for Level 1 at SLHC 1 AM for each enough-small  space-time Patterns Hits: position+time stamp All patterns inside a single chip N chips for N overlapping events identified by the time stamp Event1 AMchip1 Event2 AMchip2 Event3 AMchip3 EventN AMchipN Main problem: AM input Bandwidth, even if powerful: >10 Gbits/sec  divide the detector in thin  sectors. Each AM searches in a small 

25. SVT April 2006Alberto Annovi- IFAE 200625 SUMMARY The design and construction of SVT was a significant step forward in the technology of fast track finding We use a massively parallel/pipelined architecture combined with some innovative techniques such as the associative memory, linearized track fitting and road warrior CDF is triggering on impact parameter and collecting data leading to significant physics results B-physics, and not only, at hadron colliders substantially benefits of on-line tracking with off-line quality The system is modular and easy to upgrade The SVT technology is ready for other applications!

26. SVT April 2006Alberto Annovi- IFAE 200626 BACKUP SLIDES

27. SVT April 2006Alberto Annovi- IFAE 200627 SVX II 2.5 cm 10.6 cm 90 cm  -sector

28. SVT April 2006Alberto Annovi- IFAE 200628 AM chip internal structure DB

29. SVT April 2006Alberto Annovi- IFAE 200629 Upgrading SVT Hit Finders Merger Associative Memory Hit Buffer Track Fitter to Level 2 COT tracks fromXTRP 12 fibers hits roads hits x 12 phi sectors Sequencer raw data from SVX front end Road Warrior RW: Remove ghosts Reduce SVT processing time: c 1 +c 2 *N(Hit) +c 3 *N(Comb.) 1.More patterns  thinner roads  less fakes 2.Move Road Warrior before the HB 3.New TF++, HB++, AMS++, AM++ @ > 40MHz

30. SVT April 2006Alberto Annovi- IFAE 200630  x i Non-linear geometrical constraint for a circle: F(x 1, x 2, x 3, …) = 0 But for sufficiently small displacements: F(x 1, x 2, x 3, …) ~ a 0 + a 1  x 1 + a 2  x 2 + a 3  x 3 + … = 0 with constant a i (first order expansion of F) From non-linear to linear constraints

31. SVT April 2006Alberto Annovi- IFAE 200631 Dead Time vs. L1 Accept Rate SVT @ 0.5 x 10 32 SVT @ 3 x 10 32 UPGRADE @ 3 x 10 32

32. SVT April 2006Alberto Annovi- IFAE 200632 SVX only  Good tracks from just 4 closely spaced silicon layers  I.p. as expected due to the lack of curvature information impact parameter distribution  ~ 87  m Silicon only no XFT

33. SVT April 2006Alberto Annovi- IFAE 200633 The Device Hit Finder AM Sequencer AM Board Hit Buffer Track Fitter Detector Data Hits Super Strip Matching Patterns Roads Roads + Corresponding Hits L2 CPU Tracks + Corresponding Hits

34. SVT April 2006Alberto Annovi- IFAE 200634 Where could we insert FTK? Fast Track + few (Road Finder) CPUs Fast Track + few (Road Finder) CPUs Track data ROB Track data ROB high-quality tracks: Pt>1 GeV Ev/sec = 50~100 kHz Very low impact on DAQ PIPELINE LVL1 Fast network connection CPU FARM (LVL2 Algorithms) CALO MUON TRACKER Buffer Memory ROD Buffer Memory FE Raw data ROBs 2 nd output 1 st output No change to LVL2

35. SVT April 2006Alberto Annovi- IFAE 200635 AMS/RW status (Pisa) AMS and RW firmware implemented and tested next step implement SVT firmware tools ON SCHEDULE Pisa had the most risky responsibilities, but we are now in very good shape

36. SVT April 2006Alberto Annovi- IFAE 200636 Non italian responsabilities Pulsars –Pulsar production arrived –Large RAM mezzanine production done –Small RAM mezzanine prototype under test –ON SCHEDULE TF –First firmware written –Standalone tests starting –ON SCHEDULE HB –Firmware writing just started –BEHIND SCHEDULE –More man power (firmware engineer joined)

37. SVT April 2006Alberto Annovi- IFAE 200637 AM++ & AMSRW: A. Annovi, A. Bardi, M. Bitossi, M.Dell’Orso, P. Giannetti, P. Giovacchini, M. Piendibene, F. Spinella, L. Sartori, R. Tripiccione, S. Torre, I. Pedron, P. Catastini, S. Belforte, L. Ristori HB++: I. Furic, T. Maruyama, S. Chappa, M. Aoki, E. Berry TF++ & SRAM mezzanines: J. Adelman, U. Yang, F. Tang, M. Shochet, H. Sanders Software: R. Carosi, S. Torre, B. Simoni, A. Annovi, P. Giovacchini, M. Rescigno, B. Di Ruzza, A. Cerri, J. Bellinger, G. Volpi, F. Sforza Great support from Pulsar, DAQ, review committee, Silicon and operations people & Dervin’s group INFN & Fermilab support SVT upgrade people

38. SVT April 2006Alberto Annovi- IFAE 200638 TRIGGER: Tracking @ Level 2 & Level 1 1.Atlas/CDF USA-Pisa group working for physics case for FTK (Gruppo V –Pisa project 2000-02) @ Level 2 http://hep.uchicago.edu/cdf/shochet/ftk_12_05/meeting.html Proposal discussed during 2006 – If approved  USA funds autumn 2006 a) small prototype (using CDF AMchip) as soon as possible; b) upgrade for high luminosity; c) upgrade for SLHC Italy will be required to partecipate 2.Try to use same AMchip for simplified tracking @ Level 1

39. SVT April 2006Alberto Annovi- IFAE 200639 Save ~10  s @ 100E30 TF: RMS=18 TF++: RMS=10.7 Summer 2005 installation

40. SVT April 2006Alberto Annovi- IFAE 200640 New AM chip Standard Cell UMC 0.18  m 10x10 mm die - 5000 patterns 6 input hit buses tested up to 40 MHz, simulated up to 50 MHz 116 prototype chips on September 2004 MPW run – low yield 37% 3000 production chips on April 2005 good yield 70% private masks  better process parameter tuning for dense memory

41. SVT April 2006Alberto Annovi- IFAE 200641 AM chip & system Undoable with standard electronics (90’s)  Full custom VLSI chip - 0.7  m (INFN-Pisa) 128 patterns, 6x12bit words each Working up to 40 MHz Limit to 2-D 6 layers: 5 SVX + 1 COT ~250 micron bins  32k roads / 30 0  sector >95% coverage for P t > 2 GeV

42. SVT April 2006Alberto Annovi- IFAE 200642 Upgrade is on schedule AM++ and RW with 32k patterns have been already used in test runs for data taking Plan to install AM++ with 32k pattern in July Studies of 128k patterns coverage and efficiency are underway Plan to install TF++ as soon as it will be ready (August) then move to 128k HB++ expected to be installed during fall with 512k pattern memory Real data AM++ AMS/RW