1. Presented by, Amit Jain Pruthwin Kadmaje Giridhara Shailesh Kayambady Sathyanarayana Bhat

2. Cloud Computing

3. Problems and Risks

4. Our IDEA !!!!!

5. How the system works…. STEP 1 : RSA Key Exchange

6. STEP 2 : Encryption and Encoding in Host Lw $2,4($fp) Lw $3,8($fp) Nop Mult $2, 2 Add $4, $2,$3 Sw $2,8($fp) 0x54000000 0x00000000 0x50200004 0x00000000 0x300f2000 COMPILER (Encryption) COMPILER (Encoding) OOLMNO12 JKLMNO12 OKNMNO16 JKLMNO12 9KL2LO1J JKLMNO12 Encoded Output COMPILER (Custom ISA binary) Binary Output (Unencrypted) FINAL OUTPUT C Code Int a = b; Int c = 0; a = 2 * a; b = a + c; 0xffcdef12 0xabcdef12 0xfbedef16 0xabcdef12 Encrypted Output MIPS COMPILER

7. CODE END (PATTERN) STEP 3: Add patterns and Form packets & send OOLMNO12 JKLMNO12 …..... …. ….. …. ….. OKNMNO16 JKLMNO12 9KL2LO1J JKLMNO12 OOLMNO12 JKLMNO12 CODE BODY (PATTERN) CODE BODY (PATTERN) OOLMNO12 JKLMNO12 OKNMNO16 JKLMNO12 9KL2LO1J JKLMNO12

9. DECRYPTION STEP 4 : Packet Detection and processing I CACHE PIPELINE FIFO/ DCACHE CORE 1 CORE 2 PACKETS D CACHE PIPELINE ENCRYPTION Decoder (HW Accl)

10. FIFO/ DCACHE I CACHE PIPELINE CORE 1 PACKETS MEMORY (0-127) FIFO (128-256) TO CORE 2 PATTERN NOT FOUND !!!PATTERN FOUND !!! CODE PATTERN CODE PATTERN CODE ------------- #@$ STEP 4

11. DECRYPTION STEP 5 : Execution of Encrypted Code CORE 1 I CACHE CORE 2 D CACHE PIPELINE ENCRYPTION Decoder (HW Accl) 0xffcdef120xabcdef120xfbedef160xabcdef120x9bc2cf120xfbedef16 0xabcdef12 0x9bc2cf1a 0xebe2ef16 JKLMNO12 9KL2LO12 OKNMNO15 JKLMNO12 9KL2LO12 OKNMNO15 0xabcdef12 0x9bc2cf1a 0xebe2ef16 0xffcdef120xabcdef120xabcdef120xabcdef120x9bc2cf12 0xd12 0x55

13. DECRYPTION STEP 6 : Request Result CORE 1 I CACHE CORE 2 D CACHE PIPELINE ENCRYPTION 0xd12 0x55 55 Address 55

14. Added Security Layer ISP 2 U5 U4 U3 U2 U1 ISP 1 Use Case KEY 1 KEY 2 KEY 3 KEY 4 KEY 5 KEY A KEY B

15. WeekMilestonesStatus Week 1Instruction set Design Compiler accommodation of new instructions Hardware support for new instructions Week2Design of crypto engine Packet processing Program development Design of Pipeline of 2nd core Week 3Integration of 2 cores Perl Scripting for the automation Testing and debugging of dual core processor Week 4Addition of 2 nd level of encryption Week 5Datasheet preparation of processor Final Report and Presentation

16. References [1] Lubos Gaspar, Viktor Fischer, Lilian Bossuet, Robert Fouquet. Secure extension of FPGA softcore processors for symmetric key cryptography. 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2011, Jun 2011, Montpellier, France. [2] Eslami, Yadollah, et al. "An area-efficient universal cryptography processor for smart cards."Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 14.1 (2006): 43-56. [3] Hu, Kekai, et al. "System-level security for network processors with hardware monitors."Design Automation Conference (DAC), 2014 51st ACM/EDAC/IEEE. IEEE, 2014. [4] Fletcher, Christopher W., Marten van Dijk, and Srinivas Devadas. "A secure processor architecture for encrypted computation on untrusted programs."Proceedings of the seventh ACM workshop on Scalable trusted computing. ACM, 2012.