1. EE 5340 Semiconductor Device Theory Lecture 28 - Fall 2009 Professor Ronald L. Carter ronc@uta.edu http://www.uta.edu/ronc

2. L 28 Dec 12 e - e - e - e - e - + + + + + + + + + + + + Implanted n-channel enhance- ment MOSFET (ohmic region) 0< V T < V G V B < 0 E Ox,x > 0 Acceptors Depl Reg V S = 0 0< V D < V DS,sat n+ p-substrate Channel e- channel ele + implant ion

3. L 28 Dec 13 Si & SiO 2 AlAl Si 3 N 4 Si Si Al & SiO 2 Si 3 N 4 RangeRange RPRP Ion implantation*

4. L 28 Dec 14 “Dotted box” approx**

5. L 28 Dec 15 Calculating x i and  V T

6. L 28 Dec 16 If x i ~ x d,max

7. L 28 Dec 17 Calculating V T

8. L 28 Dec 18 Implanted V T Vt per Eq. 9.1.23 in M&K for a MOSFET with an 87-nm-thick gate oxide, Q ff /q = 10 11 cm -2, N’ = 3.5 X 10 11 cm -2, and N a = 2 X 10 15 cm -3. Both V S and V B = Figure 9.8 (p. 441)

9. L 28 Dec 19 Mobilities**

10. L 28 Dec 110 Substrate bias effect on V T (body-effect)

11. L 28 Dec 1 Body effect data Fig 9.9** 11

12. L 28 Dec 112 M&K Fig. 9.9 (Eq. 9.1.23)

13. L 28 Dec 113 Subthreshold conduction Below O.S.I., when the total band-bending < 2|  p |, the weakly inverted channel conducts by diffusion like a BJT. Since V GS >V DS, and below OSI, then N a >n S >n D, and electr diffuse S --> D Electron concentration at Source Concentration gradient driving diffusion

14. L 28 Dec 114 M&K Fig.9.10 (p.443) Band diagram along the channel region of an n-channel MOSFET under bias, indicating that the barrier qΦ B at the source depends on the gate voltage.

15. L 28 Dec 115 M&K Fig. 9.11 (p.444) Measured subthreshold characteristics of an MOS transistor with a 1.2 μm channel length. The inverse slope of the straight-line portion of this semilogarithmic plot is called the drain-current subthreshold slope S (measured in mV/decade of drain current).

16. L 28 Dec 116 Subthreshold current data Figure 11.4* Figure 10.1**

17. L 28 Dec 117 Mobility variation due to E depl Figures 11.7,8,9*

18. L 28 Dec 118 Velocity saturation effects Figure 11.10*

19. L 28 Dec 119 Based on figure 12.18* n-type channel L 0 Junction Field-Effect Transistor (JFET) Active channel height, a Ch to Substr D.R.

20. L 28 Dec 120 Pinch-off Voltage Note: In depl mode devices, V p0 > V bi

21. L 28 Dec 121 Channel conductance and drain current

22. L 28 Dec 122 N-ch. ohmic reg drain current soln.

23. L 28 Dec 123 Saturation drain current,

24. L 28 Dec 124 Ideal JFET drain characteristics IDID V DS V DS,sat I D,sat Ohmic, I D1 Non-physical analytic extension of I D1 Saturated: I D,sat ~I D1,sat

25. L 28 Dec 125 n-channel JFET gate characteristic IDID V GS VpVp I DSS Saturated: I D,sat, approx. Saturated: I D1,sat

26. L 28 Dec 126 Small-signal para- meters: g ds and g d

27. L 28 Dec 127 Graphical interpre- tation of g ds and g d IDID V DS V DS,sat I D,sat Slope = g ds Slope = g d

28. L 28 Dec 128 Small-signal gain params: g mL and g ms

29. L 28 Dec 129 Based on figure 12.18* n-type channel L 0 Channel Modulation Capacitances Active channel height, a Ch to Substr D.R.

30. L 28 Dec 130 Application of JFET theory to MESFET The channel material is often GaAs The substrate is often semi-insulating gallium arsenide (SI GaAs) V bi is replaced by V n bi, the band- bending in the semiconductor –Often limited by surface state pinning and not determined exactly by  s N eff is now exactly N ch

31. L 28 Dec 131 Final Exam EE 5340 Section 001 –8:00 to 10:30 AM –Tuesday, December 8 in –108 NH –Cover sheet will be postedon web page at http://www.uta.edu/ronc/5340/tests/ The Final is comprehensive –20% to 25% on Test 1 material –20% to 25% on Test 2 material –Balance of final on material since Test 2

32. L 28 Dec 1 References * Semiconductor Physics & Devices, by Donald A. Neamen, Irwin, Chicago, 1997. **Device Electronics for Integrated Circuits, 2nd ed., by Richard S. Muller and Theodore I. Kamins, John Wiley and Sons, New York, 1986 32