1. CSE 140: Components and Design Techniques for Digital Systems Lecture 9: Sequential Networks: Implementation CK Cheng Dept. of Computer Science and Engineering University of California, San Diego 1

2. Implementation Format and Tool Procedure Excitation Tables Example 2

3. 3 Mealy Machine: y i (t) = f i (X(t), S(t)) Moore Machine: y i (t) = f i (S(t)) s i (t+1) = g i (X(t), S(t)) C1C2 CLK x(t) y(t) Mealy Machine C1C2 CLK x(t) y(t) Moore Machine S(t) Canonical Form: Mealy and Moore Machines

4. D iClicker 4 y CLK x Q In the logic diagram below, a D flip-flop has input x and output y. A: x= Q(t), y=Q(t) B: x=Q(t+1), y=Q(t) C: x=Q(t), y=Q(t+1) D: None of the above

5. Understanding Current State and Next State in a sequential circuit 5 today sunrise Preparing for tomorrow according to our effort in today

6. C1C2 CLK x(t) y(t) Implementation Format Q(t) Q(t+1) = h(x(t), Q(t)) Circuit C1 y(t) = f(x(t), Q(t)) Circuit C2 6 Canonical Form: Mealy & Moore machines State Table  Netlist Tool: Excitation Table

7. Implementation Tool: Excitation Table 7 x(t) Q(t) CLK C1 idx(t)Q(t)Q(t+1) 0001 1110 2001 3110 State Table Find D, T, (S R), (J K) to drive F-Fs

8. Implementation Tool: Excitation Table 8 x(t) Q(t) CLK Q(t) C1 idx(t)Q(t)T(t)Q(t+1) 00011 11110 20101 31110 idx(t)Q(t)Q(t+1) 0001 1110 2011 3110 State Table Excitation Table Example with T flip flop T(t)

9. Implementation Tool: Excitation Table 9 x(t) Q(t) CLK Q(t) C1 idx(t)Q(t)T(t)Q(t+1) 00011 11110 20101 31110 Excitation Table Implement combinational logic C1 D(t), T(t), (S(t) R(t)), (J(t) K(t)) are functions of (x,Q(t))

10. Implementation: Procedure State Table => Excitation Table Problem: Given a state table, we have NS: Q(t+1) = h(x(t),Q(t)) We find D, T, (S R), (J K) to drive F-Fs from Q(t) to Q(t+1). Excitation Table: The setting of D(t), T(t), (S(t) R(t)), (J(t) K(t)) to drive Q(t) to Q(t+1). We implement combinational logic C1 D(t), T(t), (S(t) R(t)), (J(t) K(t)) are functions of (x,Q(t)). 10

11. Implementation: Procedure State Table => Excitation Table Problem: Given a state table, we have NS: Q(t+1) = h(x(t),Q(t)) We find D, T, (S R), (J K) to drive F-Fs from Q(t) to Q(t+1). Excitation Table: The setting of D(t), T(t), (S(t) R(t)), (J(t) K(t)) to drive Q(t) to Q(t+1). We implement combinational logic C1 D(t), T(t), (S(t) R(t)), (J(t) K(t)) are functions of (x,Q(t)). 11

12. Implementation: Procedure F-F State Table F-F Excitation Table 12 DTSRJK PS Q(t) NS Q(t+1) PS Q(t) DTSRJK D F-F D(t)= e D (Q(t+1), Q(t)) T F-F T(t)= e T (Q(t+1), Q(t)) SR F-F S(t)= e S (Q(t+1), Q(t)) R(t)= e R (Q(t+1), Q(t)) JK F-F J(t)= e J (Q(t+1), Q(t)) K(t)= e K (Q(t+1), Q(t))

13. State table of JK F-F: 00 0 1 01 0 10 1 11 1 0 0101 Q(t) Q(t+1) JK Excitation table of JK F-F : 0 0- 1 1- -0 0101 PS NS Q(t) Q(t+1) JK If Q(t) is 1, and Q(t+1) is 0, then JK needs to be -1. Excitation Table 13

14. Excitation Tables and State Tables 0 0- 01 1 10 -0 0101 PS NS Q(t) Q(t+1) SR Excitation Tables: 0 1 0 0101 PS NS Q(t) Q(t+1) T 00 0 1 01 0 0101 PS SR Q(t) Q(t+1) SR 10 1 11 - 0 1 0 0101 PS T Q(t) Q(t+1) T State Tables: 14

15. 0 0- 1 1- -0 0101 PS NS Q(t) Q(t+1) JK Excitation Tables: 0 1 0101 PS NS Q(t) Q(t+1) D 00 0 1 01 0 0101 PS JK Q(t) Q(t+1) JK 10 1 11 1 0 1 0101 PS D Q(t) Q(t+1) D State Tables: Excitation Tables and State Tables 15

16. Implementation: Procedure 1.State table: y(t)= f(Q(t), x(t)), Q(t+1)= h(x(t),Q(t)) 2.Excitation table of F-Fs: D(t)= e D (Q(t+1), Q(t)); T(t)= e T (Q(t+1), Q(t)); (S, R), or (J, K) 3.From 1 & 2, we derive excitation table of the system D(t)= g D (x(t),Q(t))= e D (h(x(t),Q(t)),Q(t)); T(t)= g T (x(t),Q(t))= e T (h(x(t),Q(t)),Q(t)); (S, R) or (J, K). 4.Use K-map to derive optional combinational logic implementation. D(t)= g D (x(t),Q(t)) T(t)= g T (x(t),Q(t)) y(t)= f(x(t),Q(t)) 16

17. Implementation: Example Implement a JK F-F with a T F-F 00 0 1 01 0 0101 PS JK Q(t) Q(t+1) = h(J(t),K(t),Q(t)) = J(t)Q’(t)+K’(t)Q(t) JK 10 1 11 1 0 Implement a JK F-F: Q Q’ C1 J K T 17 Q

18. id 0 1 2 3 4 5 6 7 J(t) 0 1 K(t) 0 1 0 1 Q(t) 0 1 0 1 0 1 0 1 Q(t+1) 0 1 0 1 0 T(t) 0 1 0 1 0 1 0 0101 PS NS Q(t) Q(t+1) Excitation Table of T Flip-Flop T(t) = Q(t) ⊕ Q(t+1) T(t) = Q(t) XOR ( J(t)Q’(t) + K’(t)Q(t)) Excitation Table of the Design Example: Implement a JK flip-flop using a T flip-flop T 18

19. 0 2 6 4 1 3 7 5 Q(t) J 0 0 1 1 0 1 1 0 K T(J,K,Q): T = K(t)Q(t) + J(t)Q’(t) Q Q’ J K T Example: Implement a JK flip-flop using a T flip-flop 19

20. iClicker 20 Given a flip-flop, the relation of its state table and excitation table is A.One to one B.One to many C.Many to one D.Many to many E.None of the above

21. 21 Let’s implement our free running 2-bit counter using T-flip flops S0S1S2S3S0S1S2S3 PS Next state S1S2S3S0S1S2S3S0 State Table S0S0 S0S0 S1S1 S1S1 S2S2 S2S2 S3S3 S3S3

22. 22 Let’s implement our free running 2-bit counter using T-flip flops S0S1S2S3S0S1S2S3 S1S2S3S0S1S2S3S0 State Table S0S0 S0S0 S1S1 S1S1 S2S2 S2S2 S3S3 S3S3 State Table with Assigned Encoding 0 0 1 1 0 1 Current 01 10 11 00 Next

23. 23 Let’s implement our free running 2-bit counter using T-flip flops idQ 1 (t)Q 0 (t)T 1 (t)T 0 (t)Q 1 (t+1)Q 0 (t+1) 00001 10110 21011 31100 Excitation table

24. 24 Let’s implement our free running 2-bit counter using T-flip flops idQ 1 (t)Q 0 (t)T 1 (t)T 0 (t)Q 1 (t+1)Q 0 (t+1) 0000101 1011110 2100111 3111100 Excitation table

25. 25 Let’s implement our free running 2-bit counter using T-flip flops idQ 1 (t)Q 0 (t)T 1 (t)T 0 (t)Q 1 (t+1)Q 0 (t+1) 0000101 1011110 2100111 3111100 Excitation table T 0 (t) = T 1 (t) = Q 0 (t+1) = T 0 (t) Q’ 0 (t)+T’ 0 (t)Q 0 (t) Q 1 (t+1) = T 1 (t) Q’ 1 (t)+T’ 1 (t)Q 1 (t)

26. 26 Let’s implement our free running 2-bit counter using T-flip flops idQ 1 (t)Q 0 (t)T 1 (t)T 0 (t)Q 1 (t+1)Q 0 (t+1) 0000101 1011110 2100111 3111100 Excitation table T 0 (t) = 1 T 1 (t) = Q 0 (t)

27. 27 T Q Q’ T Q Q0Q0 Q1Q1 1 T1T1 Free running counter with T flip flops T 0 (t) = 1 T 1 (t) = Q 0 (t)

28. Summary: Implementation 28 Set up canonical form Mealy or Moore machine Identify the next states state diagram ⇨ state table state assignment Derive excitation table Inputs of flip flops Design the combinational logic don’t care set utilization