1. 1 Lecture 14 Binary Adders and Subtractors

2. 2 Overview °Addition and subtraction of binary data is fundamental Need to determine hardware implementation °Represent inputs and outputs Inputs: single bit values, carry in Outputs: Sum, Carry °Hardware features Create a single-bit adder and chain together °Same hardware can be used for addition and subtraction with minor changes °Dealing with overflow What happens if numbers are too big?

3. 3 Half Adder CABS 0001 A 0 B 0 S 0 C 1 0 0 0 1 1 0 1 0 1 1 0 1 Dec Binary 1 1 +1 2 10 °Add two binary numbers A 0, B 0 -> single bit inputs S 0 -> single bit sum C 1 -> carry out

4. 4 Multiple-bit Addition A 3 A 2 A 1 A 0 0 1 A 0 1 1 1 B 3 B 2 B 1 B 0 B 0 1 0 1 1 1 A B 0 1 0 1 1 1 1 A i +B i C i SiSi C i+1 °Consider single-bit adder for each bit position. Each bit position creates a sum and carry

5. 5 Full Adder 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 C i A i B i S i C i+1 11 11 CiCi AiBiAiBi 00011110 0 1 SiSi °Full adder includes carry in C i °Notice interesting pattern in Karnaugh map.

6. 6 Full Adder 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 C i A i B i S i C i+1 S i = C i ’. A’ i. B i + C i ’. A i. B i ’ + C i. A i ’. B i ’ + C i. A i. B i °Full adder includes carry in C i °Alternative to XOR implementation

7. 7 Full Adder S i = C i ’. A i ’. B i + C i ’. A i. B i ’ + C i. A i ’. !B i ’ + C i. A i. B i S i = C i ’. (A’ I. B i + A i. B’ i ) + C i. (A’ I. B’ i + A i. B i ) S i = C’ I. (A i B i )+ C i. (A i B i )’ S i = C i (A i B i ) °Reduce and/or representations into XORs

8. 8 Full Adder (S in SOP)

9. 9 Full Adder 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 C i A i B i S i C i+1 1 111 CiCi AiBiAiBi 00011110 0 1 C i+1 °Now consider implementation of carry out °Two outputs per full adder bit (C i+1, S i ) Note: 3 inputs

10. 10 Full Adder 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 C i A i B i S i C i+1 CiCi AiBiAiBi 00011110 0 1 1 111 C i+1 C i+1 = A i. B i + C i. B i + C i. A i °Now consider implementation of carry out °Minimize circuit for carry out - C i+1

11. 11 Full Adder (C in SOP)

12. 12 Full Adder C i+1 = A i. B i + C i A i ’. B i + C i. A i. B’ i C i+1 = A i. B i + C i. (A’ I. B i + A i. B’ i ) C i+1 = A i.B i + C i.(A i B i ) Recall: S i = C i (A i B i ) C i+1 = A i.B i + C i (A i B i )

13. 13 Full Adder S i = C i (A i B i ) Half-adder C i+1 = A i B i + C i (A i B i ) °Full adder made of several half adders

14. 14 Full Adder A full adder can be made from two half adders (plus an OR gate). °Hardware repetition simplifies hardware design

15. 15 Full Adder Block Diagram °Putting it all together Single-bit full adder Common piece of computer hardware

16. 16 4-Bit Adder C 1 1 1 0 A 0 1 0 1 B 0 1 1 1 S 1 1 0 0 °Chain single-bit adders together. °What does this do to delay?

17. 17 Negative Numbers – 2’s Complement. 1 10 = 01 16 = 00000001 -1 10 = FF 16 = 11111111 128 10 = 80 16 = 10000000 -128 10 = 80 16 = 10000000 °Subtracting a number is the same as: 1.Perform 2’s complement 2.Perform addition °If we can augment adder with 2’s complement hardware?

18. 18 4-bit Subtractor: E = 1 +1 Add A to B ’ (one ’ s complement) plus 1 That is, add A to two ’ s complement of B D = A - B

19. 19 Adder- Subtractor Circuit

20. 20 Overflow in two’s complement addition °Definition: When two values of the same signs are added: Result won’t fit in the number of bits provided Result has the opposite sign. Overflow? C N-1 B N-1 A N-1 Assumes an N-bit adder, with bit N-1 the MSB

21. 21 10 1101 1010 -------- 0111 11 1110 1101 -------- 1011 01 0011 0110 -------- 1001 00 0010 0011 -------- 0101 00 0010 1100 -------- 1110 11 1110 0100 -------- 0010 Addition cases and overflow OFL 235235 3 6 -7 -2 -3 -5 -3 -6 7 2 -4 -2 4 2

22. 22 Addition cases and overflow

23. 23 Binary Parallel Adder (Again) °To add n-bit numbers: Use n Full-Adders in parallel The carries propagates as in addition by hand °This adder is called ripple carry adder °Src: Mano’s Book

24. 24 Ripple Adder Delay °How to improve?

25. 25 Carry Look Ahead Adder How to reduce propagation delay of ripple carry adders? Carry look ahead adder: All carries are computed as a function of C 0 (independent of n !) It works on the following standard principles: A carry bit is generated when both input bits Ai and Bi are 1, or When one of input bits is 1, and a carry in bit exists

26. 26 Carry Look Ahead Adder

27. 27 Carry Look Ahead Adder

28. 28 Carry Look Ahead Adder

29. 29 Carry Look Ahead Generator

30. 30 Carry Look Ahead Adder Conclusion: Each carry bit can be expressed in terms of the input carry Co, and not based on its preceding carry bit Each carry bit can be expressed as a SOP, and can be implemented using a two-level circuit, i.e. a gate delay of 2T

31. 31 Carry Look Ahead Adder

32. 32 BCD Adder °BCD digits are valid for decimal numbers 0-9 °Addition of two BCD numbers will generate an output, that may be greater than 1001 (9). °In such cases, the BCD number 0110 is added to the result as a correction step °When adding two BCD numbers, the maximum result that can be obtained is: 9 + 9 = 18 If we include a carry in bit, then the maximum result that can be obtained is: 19 (10011) Both numbers 18 and 19 are invalid BCD digits. Therefore, a 6 needs to be added to bring them to correct BCD format.

33. 33 Derivation of BCD adder

34. 34 Derivation of BCD adder °Combinations 1010 through 1111 need correction °When K=1, it is necessary to add 0110 to the binary sum

35. 35 Adding two BCD numbers – Circuit

36. 36 Binary Multiplication

37. 37 Binary Multiplication °Therefore, for multiplying two 2-bit numbers, AND gates and ADDERS will be sufficient °Half Adders

38. 38 Summary °Addition and subtraction are fundamental to computer systems °Key – create a single bit adder/subtractor Chain the single-bit hardware together to create bigger designs °The approach is call ripple-carry addition Can be slow for large designs °Overflow is an important issue for computers Processors often have hardware to detect overflow °Next time: encoders/decoder.