1. Low Power IP Design Methodology for Rapid Development of DSP Intensive SOC Platforms T. Arslan A.T. Erdogan S. Masupe C. Chun-Fu D. Thompson

2. Contents Introduction to power consumption Introduction to Main Concepts Low Power Design Methodology IP implementations Results and conclusions

3. Power Consumption in CMOS-Based DSP Systems

4. Supply Voltage Reduction Clock Gating Disadvantage: Added design effort Common Approaches to Low Power Design

5. Systematic Low Power Design Approach Exploit Algorithmic Correlations and Redundancies within an algorithm, then Map to hardware.

6. Verilog/VHDL DSP Algorithm Library Performance Criteria Block, Segmentation, etc. Multiplier SC, Bus SC CAD Synthesis Component Library Ordering algorithm Data representation Netlist Systematic Design Implementation Framework

7. Rapid Design and IP-Based Integration Platforms...... PP IP y IP x......

8. Developed IPs

9. Parameterisation Options

10. Design Flow for Filter IPs

11. FIR Filter Implementation

12. Typical Single Multiplier DSP Processor Architecture

13. Transpose Direct Form (TDF) FIR Structure

14. Modified DSP Processor Architecture for TDF FIR Filter Implementation

15. An Example SFG for IP2

16. Coefficient Memory Configuration with Coefficient Ordering Order coefficients such that adjacent coefficients are highly correlated.

17. Coefficient Word: SF : Shift Flag SF = 1 shift SF = 0 no shift PCVMA : Pre-Calculated Value Memory Address

18. Coefficient Word Decomposition (Verilog Code)

19. An Example SFG for IP3

20. Memory Operations (Verilog Code)

21. Software Implementation Example for IP3

22. Power Evaluation

23. Filter Specifications

24. Power Reductions Achieved (wordlength = 16 bit)

25. An example of a 6-tap FIR filter with block size of 3

26. Power Reductions for IP 4 (wordlength = 16 bit)

27. Reductions in Number of Memory Accesses (%)

28. Coefficient Segmentation Algorithm

29. Example Segmentations

31. Coefficient Segmentation Algorithm for Two’s Complement Coding

32. Coefficient Segmentation Algorithm for Sign-Magnitude Coding

33. Total switching activity of H and M coefficient sets with Two’s Complement Coding

34. Total switching activity of H and M coefficient sets with Sign-Magnitude Coding

35. Simplified Filter Architecture for Mixed-Mode Multiplication

36. (sign magnitude) ( Multiplier (sign) Add Acc Control Coefficient Memory Data Memory Sign  two’s Output Simplified Filter Architecture for Sign-Magnitude Multiplication

37. Example Switching Activity Distribution with Two’s Complement Coding (N=89, W=16)

38. Example Switching Activity Distribution with Sign-Magnitude Coding (N=89, W=16)

39. Power Reductions Achieved with Coefficient Segmentation

40. Power Reduction in Multiplier Circuit (wordlength = 16 bit) 47% 35% 53% 44% 62%

41. Power Reduction (wordlength = 16 bit)

42. Power Reduction at Coefficient Bus (wordlength = 16 bit) 49% 37% 54% 37% 54%

43. DCT Implementation Scheme

44. 2-D DCT Implementation Approach

45. Simplified Architecture of the DCT Processor

46. Conventional Programmable FIR Filter Architecture

47. TDF with Coefficient Ordering Programmable FIR Filter Architecture

48. Power Reduction (%)

49. IP 1 t NC Reset Load Clock DataCoefficient Output Of/ Uf Top View of IP 1

50. Block Report for IP 1

51. IP 2 t NC Reset Load Clock DataCoefficient Output Of/ Uf Top View of IP 2

52. Block Report for IP 2

53. IP 3 t NC Reset Load Clock DataCoefficient Word Output Of/ Uf Top View of IP 3

54. Block Report for IP 3

55. Area Comparison

56. Top View of IP 4 IP 4 t NC Reset Load Clock DataCoefficient Output Of/ Uf Block Size

57. IP 5 t NC Reset Load Clock DataCoefficient Word Output Of/ Uf Top View of IP 5

58. Top View of IP 6

59. Case Study: a 34-tap bandpass filter

60. Area and Power Characteristics for the Example Filter

61. Conclusions A methodology for Low Power Implementation of DSP functions has been presented. The methodology has been used to develop a number of IPs. Significant reductions in Power is reported. Power reduction is achieved in the multiplier and system buses. Methodology can be used for prototyping other DSP functions.