1. Lecture 3 CSE 341 – Microprocessors Lecture 3 Md. Omar Faruqe faruqe@bracu.ac.bd http://faculty.bracu.ac.bd/~faruqe UB 1228 faruqe@bracu.ac.bd http://faculty.bracu.ac.bd/~faruqe 1

2. Lecture 3 Notice Please email your tasks to my university email address. faruqe@bracu.ac.bdfaruqe@bracu.ac.bd Submissions to other email addresses won’t count. I use search to locate you assignments. So please make sure you use the following format: – CSE341 Task1 IdNo. – Please make sure Task1 is one word. 90% of you submitted assignment to different email address. 1 followed the format above. 2 wrote Task 1 (with a space) 1 person didn’t mention Task1 in the subject. I should have explained this clearly. 2

3. Lecture 3 Execution of Instructions Execution of instructions of an Assembly program is sequential unless you use and instruction such as Jmp. 3 The PC (Program Counter) present in a microprocessor holds the memory location of the next instruction that is to be executed.

4. Lecture 34

5. 5 Now in some cases we would like to perform operation when an external event takes place. There are two ways of monitoring this switch press Polling Interrupt

6. Lecture 3 Polling The processor checks to see if the external event has occurred at specific intervals. 6 Algorithm for polling: 1.Read P1.0 2.Is P1.0 equals to 0 ( The switch has been pressed?) a.Perform some external operation b........................................... c.................................. d................................... 3.Go to Step 1 What is the problem with this type of checking ?  Your Processors is BUSY/Tied up in the loop  You may actually miss the external even if not checked at the right time.

7. Lecture 3 Interrupts 7 The processor is automatically notified that an event has occurred. Think of the example of a phone: If your phone were on silent and you were expecting a call you would be checking at intervals to check for the call. On the other hand, if your phone has a ring tone than you could be doing anything and your phone would interrupt you and let you know that someone was calling you. The processor is automatically notified that an event has occurred.

8. Lecture 3 Interrupts Occur 8 The processor completes the current instruction its executing Saves the address of the next instruction on top of a Stack Jumps to a special location called the Interrupt Vector Table. The Interrupt Vector Table contains the address of the ISR (Interrupt Service Routine) There will be a specified ISR to handle each interrupt that they processor will come across. The ISR deals with the interrupt and takes the necessary actions as defined by the programmer. Once the ISR has been completed the processor returns to the execution of the original program. It does so by retrieving the instruction address which it saved on the top of the stack. Assembly programs use RETI to specify the return from Interrupt

9. Lecture 3 Interrupts & Priority 9 Suppose a microprocessor does three things.  Sends and receives data  Updates the display on a LED clock  Detects FIRE using a smoke alarm Suppose you were on the Phone and the Door Bell rings. What do you do ?  Ignore the Door and be on the phone  Hang up and answer the door. This is your personal preference. Microprocessors don’t have preferences, we need to set it for them. This is known as priority. What should it do if the three events occur at the same time ?

10. Lecture 3 Interrupts & Priority 10 Interrupts are a very important feature of microprocessors and modern O/S are built based on this ability of µP to use interrupts. On a µP there are generally two types of interrupts: External – Hardware based. Detected through electrical signals of special pins of the µP. Internal - o Timer-Based o Serial Communication (We will not be dealing with this). The 8051 has two pins that act can be used to detect external interrupts.

11. Lecture 3 Interrupt Structure of 8051 11

12. Lecture 3 Port 3 12

13. Lecture 3 Interrupt Priority 13 By default all the external and internal interrupts are disabled. The programmer needs to enable interrupts within the program according to needs. The activation and set up of interrupts requires manipulation of some SFRs. 8051 interrupt priority:  External Interrupt [INT0]  Timer 0  External Interrupt [INT1]  Timer 1  Serial Port

14. Lecture 3 Interrupt Vector Addresses 14 So you program is stored in memory locations 30H onwards.

15. Lecture 3 Program Memory 15 LocationsUser 00Boot strap / Microprocessor reads during start-up 03 -29Reserved Interrupt Vector Addresses 30 OnwardsYour Program

16. Lecture 3 Setup for Interrupts 16 A SFR called IE (Interrupt Enable) is used to activate interrupts. IE is a 8 bit register and can be found at memory location A8 Each of the 8 bits are allocated to the various interrupts and the register is bit addressable. Being bit addressable each of the bits can be modified separately or directly.

17. Lecture 3 IE Structure 17 EA – Enable All acts as a switch. It either turns ON/OFF all the interrupts of the µP.

18. Lecture 3 Enable Interrupt INT0 18 SETB EX0 or SETB A8H Disable Interrupt INT0 CLRB EX0 or CLRB A8H

19. Lecture 3 Setting Up Interrupts 19 Other then IE there are SFRs that need to be set. Two more SFRs are needed to set up Interrupts:  TCON – Timer Control  IP – Interrupt Priority NOTE: To use interrupts correctly on 8051 three SFRs need to be initialised and set correctly.

20. Lecture 3 TCON 20 TF1: Timer 1 Overflow Flag TR1: Timer 1 Run Control Flag IE1: External Interrupt It is set to 1 by the processor when a high-to-low edge is received on the external interrupt pin INT1. It is cleared to zero when the processor vectors to ISR [ address:0013H]. IT1: External Interrupt 1 Signal Type Control Flag It may be set to 1 by the program to enable external interrupt 1 to be triggered by a floating edge signal. It is set to 0 by the program to enable Low-Level signal triggering on external interrupt INT1.

21. Lecture 3 IP 21 PS: Serial Port Priority: Set / Cleared by the program PT1: Priority of timer 1 overflow: Set / Cleared by the program PX1: Priority of external interrupt 1: Set / Cleared by the program PT0: Priority of timer 0 overflow: Set / Cleared by the program PX0: Priority of external interrupt 0: Set / Cleared by the program Priority may be 1 for the highest or 0 for lowest. In the 8051 only the highest and the lowest may be defined The other interrupts will use the default priority If the priorities are set incorrectly the processor will revert to default values.

22. Lecture 3 Exercise 22 Write an Assembly program for the 8051 to toggle the light when the switch is pressed.

23. Lecture 3 Hint 23

24. Lecture 3 Context Switching 24 The programmer must ensure that ISR leaves the registers in the same state as they were before. For 8051 the programmer must save contents of the following:  PSW  DPTR  Register A (Acc)  Register B  Registers 00-07 How do you think this can be achieved ?

25. Lecture 3 Context Switching 25