1. DIGITAL SYSTEMS TCE1111 1 Shift Registers and Shift Register Counters Week 10 and Week 11 (Lecture 2 of 2)

2. DIGITAL SYSTEMS TCE1111 2 Shift Register is one of the most widely used functional device in Digital Systems. The simple pocket calculator illustrates the shift register’s characteristics. How Shift Register Works ? If a 4-bit shift Register receives 4-bits of parallel data and shift them to the right four positions into some other device STEP-1 1 Q D 1 Q D 0 Q D 0 Q D 0 CLOCK 0 XXXX 1 0 0 0 Parallel load a 1000: Serial receiving device CpCp CpCp CpCp CpCp CLOCK INPUT X=Undetermined State Shift Register

3. DIGITAL SYSTEMS TCE1111 3 STEP -2 STEP -3 1 Q D 0 Q D 1 Q D 0 Q D 0 CLOCK 0 XXX 0 1 0 0 0 CpCp CpCp CpCp CpCp Apply pulse 1: 1 1 Q D 0 Q D 0 Q D 1 Q D 0 CLOCK 0 XX0 0 1 0 0 0 CpCp CpCp CpCp CpCp Apply pulse 2: 2 Shift Register

4. DIGITAL SYSTEMS TCE1111 4 STEP - 4 STEP -5 1 Q D 0 Q D 0 Q D 0 Q D 1 CLOCK 0 X 0 0 0 1 0 0 0 CpCp CpCp CpCp CpCp Apply pulse 3: 3 1 Q D 0 Q D 0 Q D 0 Q D 0 CLOCK 0 0 0 0 1 1 0 0 0 CpCp CpCp CpCp CpCp Apply pulse 4: 4 Shift Register

5. DIGITAL SYSTEMS TCE1111 5 One method of identifying Shift Registers is how data is loaded into and read from the storage unit. There are Four Categories of Shift Registers. Shift Register

6. DIGITAL SYSTEMS TCE1111 6 Serial in/serial out shift register. Serial entry of data into a shift register. A 4-bit device implemented with D flip-flop. Shift Register

7. DIGITAL SYSTEMS TCE1111 7 Four bits (1010) being entered serially into the register. The register is initially clear. The 0 is put onto the data input line, when the 1 st. Clock pulse, FF0 is reset, thus storing 0. Next the 2 nd. Bit 1, is applied to the data input, making D=1 for FF0 and D=0 for FF1, when 2 nd. Clock pulse occurs, the 1 on the data input is shifted into FF0, and the 0 was in FF0 is shifted into FF1. The 3 rd. Bit, a 0 is put onto the data input line, and a clock pulse is applied, the 0 is entered into FF0, the 1 stored in FF0 is shifted into FF1, and the 0 stored in FF1 is shifted into FF2. The last bit, a 1, is now applied to the data input and a clock pulse is applied. This time the 1 is entered into FF0, the 0 stored in FF0 is shifted into FF1, the 1 stored in FF1 is shifted into FF2, and the 0 stored in FF2 is shifted into FF3. This complete the serial entry of four bits into the shift register. Shift Register

8. DIGITAL SYSTEMS TCE1111 8 Four bits (1010) being entered serially into the register.

9. DIGITAL SYSTEMS TCE1111 9 Assumed that the registers is initially cleared. Show the state of the 5-bit register for the specified data input and clock waveforms. Shift Register

10. DIGITAL SYSTEMS TCE1111 10 A serial in/parallel out shift register. Figure shows a 4-bit serial in/parallel out shift register and its logic block symbol. Shift Register

11. DIGITAL SYSTEMS TCE1111 11 Show the of the 4-bit register for the data input and clock waveforms. The register initially contains all 1’s. The register contains 0110 after 4 clock pulses. Shift Register

12. DIGITAL SYSTEMS TCE1111 12 A 4-bit parallel in/serial out shift register. Shift Register

13. DIGITAL SYSTEMS TCE1111 13 A 4-bit parallel in/serial out shift register. There are four data-input lines, D 0, D 1, D 2, D 3 and a SHIFT/LOAD input, which allows four bits of data to load in parallel into the register. When SHIFT/LOAD is LOW, gates G 1 through G 3 are enabled, allowing each data bit to be applied to the D input of its respective flip-flop. When a clock is applied, the flip-flops with D=1 will set and those with D=0 will reset, thereby storing all four bits simultaneously. When SHIFT/LOAD is HIGH, gates G 1 through G 3 are disabled and G 4 through G 6 are enabled, allowing the data bits to shift right from one stage to the next. The OR gates allow either the normal shifting operation or parallel data-entry operation, depending on which AND gates are enabled by the level on the SHIFT/LOAD input. Shift Register

14. DIGITAL SYSTEMS TCE1111 14 Show the data-output waveform for a 4-bit register with the parallel input data and the clock and SHIFT/LOAD waveforms given. Shift Register

15. DIGITAL SYSTEMS TCE1111 15 A parallel in/parallel out register. Shift Register

16. DIGITAL SYSTEMS TCE1111 16 The 74HC195 can be used for parallel in/parallel out operation. It also can be used for serial in/serial out and serial in/parallel out operation. Shift Register

17. DIGITAL SYSTEMS TCE1111 17 It can be used for parallel in/parallel out by using Q 3 as the output. When the SHIFT/LOAD input is LOW, the data on the parallel inputs are entered synchronously on the positive transition of the clock. When SHIFT/LOAD is HIGH, stored data will shift right (Q 0 to Q 3 ) synchronously with the clock. Inputs J and K are the serial data inputs to the first stage of the register (Q 0 ); Q 3 can be used for serial output data. The active-LOW clear input is asynchronous. Shift Register

18. DIGITAL SYSTEMS TCE1111 18 Sample timing diagram for a 74HC195 shift register. Shift Register

19. DIGITAL SYSTEMS TCE1111 19 4-Bit Bidirectional Shift Register-Logic Diagram Shift Register

20. DIGITAL SYSTEMS TCE1111 20 4-Bit Bidirectional Shift Register-Operation A HIGH on the control input allows data bits inside the register to be shifted to the right and a LOW enables data bits inside the register to be shifted to the left. When the control input is HIGH, gates G 1 through G 4 are enabled, and the state of the Q output of each flip-flop is passed through to the D input of the following flip-flop. When a clock pulse occurs, the data bits are shifted one place to the right. When the control input is LOW, gates G 5 through G 8 are enabled, and the Q output of each flip-flop is passed through to the D input of the preceding flip-flop. When a clock pulse occurs, the data bits are then shifted one place to the left. Shift Register

21. DIGITAL SYSTEMS TCE1111 21 4-Bit Bidirectional Shift Register-Timing Diagram Assume that initially Q0=1, Q1=1, Q2=0, and Q3=1 and the serial data-input is LOW. Timing diagram for the given control input waveform is given below: Shift Register

22. DIGITAL SYSTEMS TCE1111 22 The Johnson Counter A Johnson counter will produce a modulus of 2n. A 4-bit device has a total of 8 states and the 5-bit device has a total of 10 states. The implementation of a Johnson counter is the same regardless of the number of stages. The Q output of each stage is connected to the D input of the next stage, except the Q output of the last stage is connected back to the D input of the first stage.

23. DIGITAL SYSTEMS TCE1111 23 The Johnson Counter Clock PulseQ0Q1Q2Q3 00000 11000 21100 31110 41111 50111 60011 70001 Four-bit Johnson sequence:

24. DIGITAL SYSTEMS TCE1111 24 The Johnson Counter Clock PulseQ0Q1Q2Q3Q4 000000 110000 211000 311100 411110 501111 601111 700111 800011 900001 Five-bit Johnson sequence:

25. DIGITAL SYSTEMS TCE1111 25 The Johnson Counter

26. DIGITAL SYSTEMS TCE1111 26 The Johnson Counter Timing sequence for a 4-bit Johnson counter

27. DIGITAL SYSTEMS TCE1111 27 The Johnson Counter Timing sequence for a 5-bit Johnson counter

28. DIGITAL SYSTEMS TCE1111 28 Logic diagram for a 10-bit ring counter. The interstage connections are the same as those for a Johnson counter, except that Q rather than Q is fed back from the last stage. The Ring Counter

29. DIGITAL SYSTEMS TCE1111 29 10-bit ring counter sequence CLOCK PULSEQ0Q1Q2Q3Q4Q5Q6Q7Q8Q9 01000000000 10100000000 20010000000 30001000000 40000100000 50000010000 60000001000 70000000100 80000000010 90000000001 The Ring Counter

30. DIGITAL SYSTEMS TCE1111 30 If a 10-bit ring counter has the initial state 1010000000, determine the waveform for each of the Q outputs. The Ring Counter