1. Testing of logic arrayes to be programmed Levels of abstraction While I>k then.. ROM ALU RAM & &1 Behavioural model Functional model Logic level model Electric level modell Geometric model Level of abstraction increases Ability to localise/discover an error increases Tests (stimula) can be generated at the level where the hardware to be realised is described. Usually it is possible to use either logical, functional or behavioural level model.

2. Boundary Scan TI TO Elements of memory (triggers) The concept of boundary scanning There are triggers between the logic and each output of every microcircuit within the system. It is possible to connect the triggers into a single shift register. Thus it is possible to test each microcircuit separately, of course, in a specialised mode.

3. BoundaryScan Cell MUX S 1 0 ShiftDR Scan In (SI) T D T D MUX S 1 0 Mode Data Out (PO) ClockDRUpdateDR Shift Register Parallel Output Register Scan Out (SO) Data In (PI)

4. Modes of Boundary Scan Cell I MUX S 1 0 ShiftDR Scan In (SI) T D T D MUX S 1 0 Mode Data Out (PO) ClockDRUpdateDR Shift Register Parallel Output Register Scan Out (SO) Data In (PI) MUX S 1 0 ShiftDR Scan In (SI) T D T D MUX S 1 0 Mode Data Out (PO) ClockDRUpdateDR Shift Register Parallel Output Register Scan Out (SO) Data In (PI) Normal Mode Update Mode

5. Modes of Boundary Scan Cell II MUX S 1 0 ShiftDR Scan In (SI) T D T D MUX S 1 0 Mode Data Out (PO) ClockDRUpdateDR Shift Register Parallel Output Register Scan Out (SO) Data In (PI) MUX S 1 0 ShiftDR Scan In (SI) T D T D MUX S 1 0 Mode Data Out (PO) ClockDRUpdateDR Shift Register Parallel Output Register Scan Out (SO) Data In (PI) Capture Mode Shift Mode

6. IEEE 1149.1 Device Architecture Core Logic MUX TDI TDO Bypass Identification Register Instruction Register TAP (Test Access Port) Controller (Test Data In) (Test Data Out) Test Reset (Optional)

7. L0L0 L1L1 LiLi L n-1 LiLi XX Y Y W W XX Y W W Y IN OUT Iterative logic arrays -The elements of the array are identical and the regularity gives certain additional possibilities for testing An one-dimensional array is given as an example, but the same case applies also for two-dimensional arrays.

8. Test (one element) The transport of the effect of the fault to the observed output. (through k-element) Restoration (m elements) In the case of C-tested array the duration of the test does not depend upon the number of elements in the array. C-testability... Test (one element) It is possible to realise one test on all elements of the array by k+m+1 steps, notwithstanding the number of the elements (i.e. dimensions of the array). If it is possible to do it with all tests we have C-tested array.

9. Example Test for one element in the array LiLi 0 1 0 0 0/1 0 Due to faults, 0 in the right hand side output may turn into 1 The possible effect of the fault must be brought to the observed output (in this example – down) L i+1 L i+2 0/1 0 1 0 1/0 1 0 0 0 In order to apply the same test to some following element we must restore the original value of the test after having brought the effect of the fault to the observed output. On the right hand side there must be the combination 0 1. L i+3 L i+4 0 0 1 0 1 1 0 0 1 0

10. Example...continued LiLi 0 1 0 0/1 0 01 0 1/0 1 0 0 0 1 0 1 1 0 0 1 0 L i+1 L i+2 LiLi LiLi LiLi 0 0/1 0 0 Test (one element) The transport of the effect of the fault to the observed output. (through 2 elements) Restoration (2 elements) Test (one element) It took five steps to realise the test on the whole of the array notwithstanding its size (number of elements)

11. It took five steps to realise the test on the whole of the array notwithstanding its size (number of elements). Example...continued

12. COMPARATOR (comparison circuit) Functional/faulty I-testability

13. CI-testability