1. Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Topics n Transistor sizing: –Spice analysis. –Logical effort.

2. Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Transistor sizing n Not all gates need to have the same delay. n Not all inputs to a gate need to have the same delay. n Adjust transistor sizes to achieve desired delay.

3. Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Example: adder carry chain + + aiai bibi aiai cici bibi cici bibi aiai bibi aiai c i+1 One stage: c i+1 =a i b i + (a i + b i ) c i c i+1

4. Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Carry chain optimization n Connect four stages. n Optimize delay through carry chain by selecting transistor sizes.

5. Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Case 1 W/L for all stages: n = 0.75/0.5, p = 1.5/0.5

6. Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Case 2 Wider pulldowns for first stage XOR, larger first stage inverter:

7. Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Case 3 Larger transistors in second and third stages:

8. Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Inter-stage effects in transistor sizing n Increasing a gate’s drive also increases the load to the previous stage: Larger drive Larger load

9. Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Logical effort n Logical effort is a gate delay model that takes transistor sizes into account. n It is measured by the ratio of the input capacitance of a gate to the input capacitance of an inverter that delivers the same output current. (From Weste and Harris, p. 166, CMOS, VLSI Design.) n Allows us to optimize transistor sizes over combinational networks.

10. Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Logical effort gate delay model Gate delay is measured in units of minimum-size inverter delay . n Gate delay formula: –d = f + p. n Effort delay f is related to gate’s intrinsic work to compute its logic output. n Parasitic delay p depends on gate’s structure.

11. Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Effort delay n Effort delay has two components: –f = gh. n Electrical (fanout) effort h is determined by gate’s load: –h = C out /C in n Logical effort g is determined by gate’s function and structure.

12. Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Logical effort The logical effort values are derived from the n and p-transistor sizes of the gates, and are specified per each input. The denominator term, 3, comes from the sum of the channel widths of the n and p-transistor which is a measure of the gate capacitor (input capacitance). The numerator terms are the sums of the channel widths of the respective gates. For a more in depth discussion, please see http://www-md.e-technik.uni-rostock.de/lehre/vlsi_ii/Harris/LogicalEffort.pdf

13. Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Logical effort along a path n Logical effort along a chain of gates: –G =  g i. n Total electrical (fanout) effort along path depends on ratio of first and last stage capacitances: –H = C out /C in.

14. Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Branching effort n Takes into account fanout. n Branching effort at one stage: –b = (C onpath + C offpath / C onpath ) n Branching effort along path: –B =  b i.

15. Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Path delay n Path effort: –F = GBH. n Path delay is sum of delays of gates along the path: –D =  g i h i +  p i = D F + P.

16. Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Sizing the transistors n Optimal buffer chains are exponentially tapered: –f^ = F 1/N. n Determine W/L of each gate on path by working backward from the last gate: –C in,i = g i C out,i / f^

17. Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Example: logical effort n Size transistors in a chain of three two-input NAND gates. –First NAND is driven by minimum-size inverter. –Last NAND is connected to 4X inverter.

18. Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Example, cont’d. n Logical effort G = 4/3 * 4/3 * 4/3. n Branching effort = 1. n Electrical effort = 4. n F = G B H = 9.5. n Optimum effort per stage f^ = 2.1. n Delay = 3*2.1 = 6.3