1. EE141 Combinational Circuits 1 Chapter 6 (I) Designing Combinational Logic Circuits Static CMOSStatic CMOS Pass Transistor LogicPass Transistor Logic V1.0 4/25/03 V2.0 5/4/03 V3.0 5/15/03

2. EE141 Combinational Circuits 2 Revision Chronicle  5/2: Add some NAND8 figures (to compare NAND8 circuits) from old Weste textbook to this slide.  5/4:  Add 4 Pass-Transistor Logic Slides from Weste textbook  Split Chapter 6 into two parts: Part I focuses on Static and Pass Transistor Logic. Part II focuses on Dynamic Logic  5/15:  Add the Transmission Gate slides (x5) from Kang’s textbook

3. EE141 Combinational Circuits 3 Combinational vs. Sequential Logic CombinationalSequential Output = f ( In ) Output = f ( In, Previous In )

4. EE141 Combinational Circuits 4 Static CMOS Circuits At every point in time (except during the switching transients) each gate output is connected to either via a low-resistive path (PUN, PDN) The outputs of the gates assume at all times the value of the Boolean function, implemented by the circuit (ignoring the transient effects during switching periods). This is in contrast to the dynamic CMOS circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes. V DD orV ss

5. EE141 Combinational Circuits 5 Static Complementary CMOS Pull-up Network (PUN) and Pull-down Network (PDN) are Dual Logic Networks V DD F(In1,In2,…InN) In1 In2 InN In1 In2 InN PUN PDN PMOS only (good for transfer 1) NMOS only (good for transfer 0) … …

6. EE141 Combinational Circuits 6 Threshold Drops in NMOS and PMOS -- Check Candidates for PUN and PDN V DD V DD  0 PDN 0  V DD CLCL CLCL PUN V DD 0  V DD - V Tn CLCL V DD V DD  |V Tp | CLCL S DS D V GS S SD D G G G G

7. EE141 Combinational Circuits 7 Complementary CMOS Logic Style

8. EE141 Combinational Circuits 8 NMOS Transistors in Series/Parallel Connection Transistors can be thought as a switch controlled by its gate signal NMOS switch closes when switch control input is high

9. EE141 Combinational Circuits 9 PMOS Transistors in Series/Parallel Connection

10. EE141 Combinational Circuits 10 Example 1: NAND2 Gate (Use DeMorgan’s Law)

11. EE141 Combinational Circuits 11 Example2: NOR2 Gate

12. EE141 Combinational Circuits 12 Design of Complex CMOS Gate D A BC D A B C

13. EE141 Combinational Circuits 13 Constructing a Complex Gate SN1 SN2

14. EE141 Combinational Circuits 14 Static CMOS Properties  Full rail-to-rail swing: High noise margins  Logic levels not dependent upon the relative device sizes: Ratioless  Always a path to Vdd or GND in steady state: Low output impedance  Extremely high input resistance; nearly zero steady- state input current (input to CMOS gate)  No steady-state direct path between power and ground: No static power dissipation  Propagation delay function of output load capacitance and resistance of transistors

15. EE141 Combinational Circuits 15 Switch Delay Model A R eq A RpRp A RpRp A RnRn CLCL A CLCL B RnRn A RpRp B RpRp A RnRn C int B RpRp A RpRp A RnRn B RnRn CLCL NAND2 INV NOR2

16. EE141 Combinational Circuits 16 Input Pattern Effects on Delay  Delay is dependent on the pattern of input (Assume Rp = 2 Rn for same size of transistors)  Low-to-high transition:  Both inputs go low –Delay is 0.69 (Rp/2) CL  One input goes low –Delay is 0.69 (Rp) CL  High-to-low transition:  Both inputs go high (required for NAND) –Delay is 0.69 (2R n )CL CLCL B RnRn A RpRp B RpRp A RnRn C int

17. EE141 Combinational Circuits 17 Transistor Sizing CLCL A RnRn A RpRp B RpRp B RnRn C int B RpRp A RpRp A RnRn B RnRn CLCL 2222 22 1 1 4444 Assumes Rp = 2Rn at same W/L NAND is preferred than NOR implementation!!

18. EE141 Combinational Circuits 18 Delay Dependence on Input Patterns A=B=1  0 A=1, B=1  0 A=1  0, B=1 time [ps] Voltage [V] Input Data Pattern Delay (psec) A=B=0  1 69 A=1, B=0  1 62 A= 0  1, B=1 50 A=B=1  0 35 A=1, B=1  0 76 A= 1  0, B=1 57 NMOS = 0.5  m/0.25  m PMOS = 0.75  m/0.25  m C L = 100 fF A=1, B=1  0 (for both Cint and C L ) A=1, B=0  1 (Consider Body effect) NAND2 is true OUT connects to GND

19. EE141 Combinational Circuits 19 Transistor Sizing a Complex CMOS Gate OUT = D + A (B + C) D A BC D A B C 1 2 22 4 4 8 8

20. EE141 Combinational Circuits 20 Fan-In Considerations 4-input NAND Gate

21. EE141 Combinational Circuits 21 Fan-In Considerations DCBA D C B A CLCL C3C3 C2C2 C1C1 Distributed RC model (Elmore delay) t pHL = 0.69(R 1 C 1 +(R 1 +R 2 )C 2 + (R 1 +R 2 +R 3 )C 3 + (R 1 +R 2 +R 3 +R 4 )C L =0.69 R eqn (C 1 +2C 2 +3C 3 +4C L ) Propagation (H  L) delay deteriorates rapidly as a function of fan-in no. : Quadratically in the worst case. R4 R3 R2 R1

22. EE141 Combinational Circuits 22 t p as a Function of Fan-In t pL H t p (psec) fan-in t pH L Quadratic (H->L) tptp (L  H) Linear Increase in Intrinsic Capacitance, Assume Only one PMOS is On for critical case

23. EE141 Combinational Circuits 23 (tpHL, tpLH) as a Function of Fan-Out Gates with a fan-in greater than or equal to 4 becomes excessively slow and should be avoided!

24. EE141 Combinational Circuits 24 t p as a Function of Fan-In and Fan-Out  Fan-in: quadratic due to increasing resistance and capacitance  Fan-out: each additional fan-out gate adds two gate capacitances to C L To the preceding stage)

25. EE141 Combinational Circuits 25 Fast Complex Gates: Design Technique 1  Transistor sizing  Increase Intrinsic parasitic cap and create CL of the preceding stage  Progressive sizing In N CLCL C3C3 C2C2 C1C1 In 1 In 2 In 3 M1 M2 M3 MN Distributed RC line: M1 > M2 > M3 > … > MN (the FET closest to the output is the smallest) Not simple in Layout!

26. EE141 Combinational Circuits 26 Fast Complex Gates: Design Technique 1

27. EE141 Combinational Circuits 27 Fast Complex Gates: Design Technique 2  Input reordering: Put late arrival signal near the output node. C2C2 C1C1 In 1 In 2 In 3 M1 M2 M3 CLCL C2C2 C1C1 In 3 In 2 In 1 M1 M2 M3 CLCL critical path charged 1 0101 1 Delay determined by time to discharge C L, C 1 and C 2 Delay determined by time to discharge C L 1 1 0101 charged discharged

28. EE141 Combinational Circuits 28 Fast Complex Gates: Design Technique 3  Logic Restructuring In general, C > B > A in speed (A) (B) (C) F =NAND8 Gate

29. EE141 Combinational Circuits 29 Design Technique 3: Logic Restructuring (from Neil Weste, 2 nd Ed, 93) Tradeoff between Area and Speed (and Power?)

30. EE141 Combinational Circuits 30 Fast Complex Gates: Layout Technique (A) (B) (A): 4 internal cap 2 output diff cap (B): 4 internal cap 4 output diff cap (A) Is better than (B)

31. EE141 Combinational Circuits 31 Optimizing Performance in Combinational Networks For given N: C i+1 /C i = C i /C i-1 To find N: C i+1 /C i ~ 4 How to generalize this to any combinational logic path? E.g., How do we size the ALU datapath to achieve maximum speed? CLCL In Out 1 2 N (in units of  inv )

32. EE141 Combinational Circuits 32 Logical Effort  Inverter has the smallest logical effort and intrinsic delay of all static CMOS gates  Logical effort of a gate presents the ratio of its input capacitance to the inverter capacitance when sized to deliver the same current  Logical effort increases with the gate complexity

33. EE141 Combinational Circuits 33 Logical Effort Logical effort is the ratio of input capacitance of a gate to the input capacitance of an inverter with the same output current g = 1 g = 4/3 g = 5/3

34. EE141 Combinational Circuits 34 Logical Effort From Sutherland, Sproull

35. EE141 Combinational Circuits 35 Estimated Intrinsic Delay Factor

36. EE141 Combinational Circuits 36 Logical Effort p – intrinsic delay : gate parameter g – logical effort : gate parameter f – effective fanout Normalize everything to an inverter: g inv =1, p inv = 1 Divide everything by  inv (everything is measured in unit delays  inv ) (Assume  = 1)

37. EE141 Combinational Circuits 37 Delay in a Logic Gates Gate delay: d = h + p Effort delay Intrinsic delay Effort delay: h = g f Logical Effort Effective fanout = C out /C in Logical effort is a function of topology, independent of sizing Effective fanout (electrical effort) is a function of load/gate size

38. EE141 Combinational Circuits 38 Logical Effort of Gates

39. EE141 Combinational Circuits 39 Logical Effort of Gates Fan-out (f) Normalized delay (d) t 1234567 pINV t pNAND F(Fan-in) g = 1 p = 1 d = f+1 g = 4/3 p = 2 d = (4/3)f+2

40. EE141 Combinational Circuits 40 Add Branching Effort Branching effort:

41. EE141 Combinational Circuits 41 Multistage Logic Networks Stage Effort: h i = g i f i Path Electrical Effort: F = C out /C in Path Logical Effort: G = g 1 g 2 …g N Branching Effort: B = b 1 b 2 …b N Path effort (total): H = GFB Path delay (total) D =  d i =  p i +  h i

42. EE141 Combinational Circuits 42 Optimum Effort per Stage When each stage bears the same effort: Minimum path delay Effective fanout of each stage: Stage efforts: g 1 f 1 = g 2 f 2 = … = g N f N

43. EE141 Combinational Circuits 43 Optimal Number of Stages For a given load, and given input capacitance of the first gate Find optimal number of stages and optimal sizing Substitute ‘best stage effort’

44. EE141 Combinational Circuits 44 Example: Optimize Path g = 1 f = a g = 5/3 f = b/a g = 5/3 f = c/b g = 1 f = 5/c Effective fanout, F = 5 G = 25/9 H = GF=125/9 = 13.9 h = 1.93 (optimal stage effort) = a = 1.93 b = ha/g 2 = 2.23 c = hb/g 3 = 5g 4 /f = 2.59

45. EE141 Combinational Circuits 45 Example – 8-input AND

46. EE141 Combinational Circuits 46 Method of Logical Effort  Compute the path effort: F = GBH  Find the best number of stages N ~ log 4 F  Compute the stage effort f = F 1/N  Sketch the path with this number of stages  Work either from either end, find sizes: C in = C out *g/f Reference: Sutherland, Sproull, Harris, “Logical Effort, Morgan-Kaufmann 1999.

47. EE141 Combinational Circuits 47 Summary Sutherland, Sproull Harris

48. EE141 Combinational Circuits 48 Pass-Transistor Logic

49. EE141 Combinational Circuits 49 Pass-Transistor Logic

50. EE141 Combinational Circuits 50 Pass Transistor Logic Basics Logic Function: B B A F =AB + 0B = AB 0 Example: AND Gate A, B: A is Input signal, B is the Control Signal

51. EE141 Combinational Circuits 51 Example: Design of XNOR2 (b) Pass-network Karnaugh map A as the control signals B as the passed signals (a) Truth table (c) Logic function

52. EE141 Combinational Circuits 52 Example: Implementation of XNOR2 (a)Transmission Gate (b)NMOS (c)Cross-couple

53. EE141 Combinational Circuits 53 Example2: Construct Boolean Functions Example2: Construct Boolean Functions Implement: Truth Table:

54. EE141 Combinational Circuits 54 NMOS-Only Logic 00.511.52 0.0 1.0 2.0 3.0 Time [ns] V o l t a g e [V] x Out In Suffer from Vt degradation (Vx = Vdd- Vt(x)) Body effect (Vsb, Vx has value and Vt(x) is bigger than Vt(0))

55. EE141 Combinational Circuits 55 NMOS-only Switch A =2.5 V B C =2.5 V C L A =2.5 V C =2.5 V B M 2 M 1 M n Threshold voltage loss causes static power consumption V B does not pull up to 2.5V, but 2.5V - V TN NMOS has higher threshold than PMOS (body effect)

56. EE141 Combinational Circuits 56 NMOS Only Logic: Level Restoring Transistor M 2 M 1 M n M r Out A B V DD V Level Restorer X Advantage: Full Swing Restorer adds capacitance, takes away pull down current at X Ratio problem among (Mr and Mn)

57. EE141 Combinational Circuits 57 Restorer Sizing 0100200300400500 0.0 1.0 2.0 W/L r =1.0/0.25 W/L r =1.25/0.25 W/L r =1.50/0.25 W/L r =1.75/0.25 V o l t a g e [V] Time [ps] 3.0 Upper limit on Restorer Transistor size

58. EE141 Combinational Circuits 58 Solution 2: Single Transistor Pass Gate with V T =0 Out V DD V 2.5V V DD 0V0V 2.5V 0V0V WATCH OUT FOR LEAKAGE CURRENTS

59. EE141 Combinational Circuits 59 Complementary/Differential Pass Transistor Logic (CPL/DPL)

60. EE141 Combinational Circuits 60 Differential Cascode Voltage Switch Logic (DCVSL) (p.267) V DD V SS PDN1 Out V DD V SS PDN2 Out A A B B M1M2 Differential Cascode Voltage Switch Logic (DCVSL)

61. EE141 Combinational Circuits 61 DCVSL Example

62. EE141 Combinational Circuits 62 DCVSL Transient Response Time [ns] V o l t a g e [V] A B A,B A,B

63. EE141 Combinational Circuits 63 Solution 3: Use of Transmission Gate A B C C A B C C B C L C = 0 V A =2.5 V C =2.5 V

64. EE141 Combinational Circuits 64 Analysis of TG (Transmission Gate) PMOS: NMOS: G G S S D D

65. EE141 Combinational Circuits 65 Analysis of TG (I)

66. EE141 Combinational Circuits 66 Analysis of TG (II)

67. EE141 Combinational Circuits 67 Resistance of Transmission Gate

68. EE141 Combinational Circuits 68 Application1: Inverting 2-to-1 Multiplexer GND V DD AB S S S S F

69. EE141 Combinational Circuits 69 Application2: 6-T(ransistor) XOR Gate BAF 000 011 101 110 Truth Table A B F B A B B M1 M2 M3/M4 B=0: Pass A Signal B=1: Inverting A Signal 6T has the inverter of B

70. EE141 Combinational Circuits 70 Application3: Transmission Gate Full Adder (to be discussed in Chapter 11) Similar delays for Sum and Carry

71. EE141 Combinational Circuits 71 Delay in Transmission Gate Networks C R eq R CC R C In m (c)

72. EE141 Combinational Circuits 72 Delay Optimization Buffer can be (a)Inverter pairs (b)One inverter + Final correcting inverter

73. EE141 Combinational Circuits 73 Summary  Fan-in and Fan-out of gates play an important role in CMOS circuit speed.  Concept of Logic Efforts can generalize the invert chain design to complex gate chain design.  Pass Transistor Logic leads low-power, low- footprint designs, but it should be used with special care.