1. RICH2 support and cooling mechanics status update Massimo Benettoni July 30, 2014 1

2. “In progress” proposal for EC and DEB support: Structure composed by a cold aluminum structural bar Support of harness integrated with cold bar In case of arrangement by rows: independent cables and cable trays support bar Possible technologies for cold bar production: - extruded bars / profiles (require custom mold) - machined bars + deep drilling - diam. >7 mm x 1.4m long … ~ ok 2

3. Harness support - Tx and Rx mounted on a harness support (board?) - Tx/Rx un/plugged sliding back/forth the support on side rails - possible cables support bar to stand cables and cable-trays weight - HV connectors support t.b.defined DEBs maintenance scenario: - unplug and remove EC HV cables - slide back Tx/Rx support to decouple from DEB (stroke ~ 1 cm) - unscrew & slide back DEB to decouple connectors from backboard (stroke ~8 mm) - detach DEB from cold support bar (simultaneous rotation + displacement) 3

4. EC fixing to flange bar Two design to be tested to fix EC to cold flange: - axially from back, 4x M2.5 screws - 4 wings overlapping cold bar, M2.5 screws backboard design agreed step file exchanged redundant machining... Thermal coupling backboards to coldbar required to cool Claros? E.g. die-cut thermal pads. Pressure on backboard? Thickness? Safety/fire specs? E.g. Bergquist Gap Pad, 3000S30 Fujipoly Sarcon, 3M catalog... 4

5. Tx DCDC Tx Rx DEBs with heating components facing the structure, sandwiched to an interface plate, Interface plate machined to match different chips high. Thermal pads interposed between interface plate and hot chips. components thick > 7 mm placed along the DB border.. possible?...in order to avoid interferences with cold bar. DC/DC along border, oriented as sketched ….. possible? Relaxed DEb layout : 130 mm high vs 115mm of Steve layout Steve layout March31 Interface plate With thermal pads DCDC FPGA GBT DCDC FPGA GBT Very zipped version..rich1 only?

6. PMTs HV connection - exit from EC along plate sides should be possible with wires diameter up to 2 mm - if pigtail, HV cables routing on top DEBs+blade sandwich - to replace DEBs: disconnect up to … 16 single HV cables - possible to distribute HV cables on both sides of EC - HV connector fixed on harness …. t.b.defined … -HV bus below backboard seems not feasible, missing space for connector 6

7. Summary EC fixing to flange bar with M2 ~ M2.6 screws to be verified if adequate Backup solution: fixing with 4 long fins as Christoph proposal arrangement of components on DEBs to be iterated/confirmed HV pigtails as proposed on May 8 should be feasible with cables up to ~ 2 mm diameter HV bus to be investigated? Tricky design but easier maintenance scenario. Prototypes of structure required to confirm feasibility, stability, precision 7

8. Thermal simulations update Input loads per PMT assumed ~ 3.2 W: - baseboard 0.4W - Claros 16x8 mW - FPGA1.5 W - GBT0.5 W - DC/DC0.7 W T=0 imposed to the cooling duct wall Neglected: contact resistances, convection, irradiation, “pure” aluminum parts, Cooling of DEb and DC/DC depending on thermal pad / thermal contact, seems predictable.. ok Cooling of Claros and baseboard depends on pcb boards (and connectors!!!) conductivity: ??? Connectors: here assumed same  of boards … E.g. FR4/G10  0.3 W/mK What can be influence of copper planes, tracks, vias on board conductivity? E.g. - FEb & Bb: on plane assuming 2x35 um Cu / 1.6 mm thickness => ~ 4.5% of Cu: = 18 W/mk - Baseb: 6 x 105 um thick planes, but plenty of holes … assuming 300 um Cu / 3 mm thickness => 10% of Cu: on plane = 40 W/mk -  through thickness? Is it affected by vias etc...? guess from 0 to 1% of Cu: = 0.3 – 4 W/mK => conductivity of pcbs change dramatically considering Cu content … very uncertain values!

9. Neglecting Cu:  =0.3 W/mK =>  t = 82°C on Claro! =boards 18&0.3, BB 40&2 W/mk=>  t = 4.5°C Full model: =boards 18&0.3, BB 40&2 W/mk=>  t = 10°C on DCDC E.g. Reducing estimated  of all pcbs by a factor 4 =>  t = 11.5°C on Claro and BB

10. Conclusions RICH2 support structure baseline design need to be iterated, e.g. wrt to board layout Cooling of Voltage dividers (thus PMTs) depend strongly on BB conductivity Cooling of Claros depend strongly on Feb, backb and connectors conductivity Claros: very low power but may be very well insulated..high temperature + convection Expected max temperature about 12 ° C wrt cooling duct wall (t.b.verified, w.r.t contact resistances … etc..) Next : mostly on test beam setup design …..