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Incorporating Driver Sizing Into Buffer Insertion Via a Delay Penalty Technique Chuck Alpert, IBM Chris Chu, Iowa State Milos Hrkic, UIC Jiang Hu, IBM Stephen Quay, IBM Gopal Gandham, IBM Chandramouli Kashyap, IBM
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2 Which One is Not Like the Others?
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3 Buffer insertion Driver sizing Wire sizing Steiner tree BIWS
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4 Why Simultaneous Optimization? Electrically-challenged net Driver sizing alone Buffer insertion alone Simultaneous optimization
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5 Integrating Driver Sizing Three choices
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6 Driver Sizing Affects Multiple Nets slow stage
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7 Upstream Capacitance Effects Slack (ns) # Nets Optimized
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8 The Driver Sizing Penalty C1C1C1C1 C2C2C2C2 C1C1C1C1 Decoupling buffers Penalty is delay through fastest decoupling buffer/inverter chain
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9 Delay Penalty Algorithm Continuous buffer library not realizable Assume set of discrete buffers B1,..., Bn such that C B1 < C B2 <... < C Bn monotone function delay(Bi, C) Apply dynamic programming
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10 Example B1B1 Given optimal chains B2B2 B3B3 B4B4 C B5 Find optimal chain for B5
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11 Dynamic Programming Recurrence To drive capacitance C Bi, combine optimal chain driving C Bj with buffer Bj D(C B1 )=0 D(C Bi )=min 0<j<i {D(C Bi ) + Delay(Bj, C Bi )}
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12 Advantages O(n 2 ) complexity Compute once as a lookup table Can handle inverters and slew Virtually no CPU cost Applicable for many approaches
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13 Experiments Five unoptimized circuits (73 – 303K cells) Three approaches VG (no driver sizing) Max (driver sizing with no delay penalty) DP (driver sizing with delay penalty) Run on thousands of nets
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14 Total Buffers Inserted
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15 Number of Upsized drivers
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16 Total Area Percentage Increase
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17 Worst Slack
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18 And So... Simple to combine buffer insertion with driver sizing Virtually no CPU impact Extends to many buffer insertion approaches No timing graph queries Works well
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