1. Penn ESE370 Fall2014 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 15: October 3, 2014 Scaling

2. Penn ESE370 Fall2014 -- DeHon 2 Today VLSI Scaling Trends/Disciplines Effects Alternatives (cheating)

3. Penn ESE370 Fall2014 -- DeHon 3 Scaling Premise: features scale “uniformly” –everything gets better in a predictable manner Parameters:   (lambda) -- Mead and Conway (Day14)  F -- Half pitch – ITRS (F=2 )  S – scale factor –  Rabaey  F ’ =S×F

4. Penn ESE370 Fall2014 -- DeHon 4 ITRS Roadmap Semiconductor Industry rides this scaling curve Try to predict where industry going –(requirements…self fulfilling prophecy) http://public.itrs.net

5. Preclass 1 Scaling from 32nm  22nm? Penn ESE370 Fall2014 -- DeHon 5

6. 6 MOS Transistor Scaling (1974 to present) S=0.7 [0.5x per 2 nodes] Pitch Gate Source: 2001 ITRS - Exec. Summary, ORTC Figure [from Andrew Kahng]

7. Penn ESE370 Fall2014 -- DeHon 7 Half Pitch (= Pitch/2) Definition (Typical MPU/ASIC) (Typical DRAM) Poly Pitch Metal Pitch Source: 2001 ITRS - Exec. Summary, ORTC Figure [from Andrew Kahng]

8. Penn ESE370 Fall2014 -- DeHon 8 250 -> 180 -> 130 -> 90 -> 65 -> 45 -> 32 -> 22 -> 16 0.5x 0.7x NN+1N+2 Node Cycle Time (T yrs): *CARR(T) = [(0.5)^(1/2T yrs)] - 1 CARR(3 yrs) = -10.9% CARR(2 yrs) = -15.9% * CARR(T) = Compound Annual Reduction Rate (@ cycle time period, T) Log Half-Pitch Linear Time 1994 NTRS -.7x/3yrs Actual -.7x/2yrs Scaling Calculator + Node Cycle Time: Source: 2001 ITRS - Exec. Summary, ORTC Figure [from Andrew Kahng]

9. Penn ESE370 Fall2014 -- DeHon 9 Scaling Channel Length (L) Channel Width (W) Oxide Thickness (T ox ) Doping (N a ) Voltage (V)

10. Penn ESE370 Fall2014 -- DeHon 10 Full Scaling Channel Length (L) S Channel Width (W) S Oxide Thickness (T ox ) S Doping (N a ) 1/S Voltage (V) S

11. Penn ESE370 Fall2014 -- DeHon 11 Effects on Physical Properties? Area Capacitance Resistance Threshold (V th ) Current (I d ) Gate Delay (  gd ) Wire Delay (  wire ) Power Go through full (ideal) …then come back and ask what still makes sense today.

12. Penn ESE370 Fall2014 -- DeHon 12 Area     S  Area impact?   L × W     S 2  32nm   22nm  50% area  2× capacity same area S=0.7 [0.5x per 2 nodes] Pitch Gate L W

13. Penn ESE370 Fall2014 -- DeHon 13 Capacity Scaling from Intel

14. Penn ESE370 Fall2014 -- DeHon 14 Capacitance Capacitance per unit area scaling? –C ox =  SiO 2 /T ox –T ox   S×T ox –C ox   C ox /S

15. Penn ESE370 Fall2014 -- DeHon 15 Capacitance Gate Capacitance scaling?  C gate = A×C ox     ×S 2  C ox   C ox /S  C gate   S×C gate

16. Penn ESE370 Fall2014 -- DeHon 16 Resistance Resistance scaling? R=  L/(W*t) W   S×W L, t similar R   R/S

17. Penn ESE370 Fall2014 -- DeHon 17 Threshold Voltage V TH   S×V TH

18. Penn ESE370 Fall2014 -- DeHon 18 Current Which Voltages matters here? (V gs,V ds,V th …) Transistor charging looks like voltage-controlled current source Saturation Current scaling? I d =(  C OX /2)(W/L)(V gs -V TH ) 2 V gs= V   S×V V TH   S×V TH W   S×W L   S×L C ox   C ox /S I d   S×I d

19. Penn ESE370 Fall2014 -- DeHon 19 Current Velocity Saturation Current scaling? V gs= V   S×V V TH   S×V TH L   S×L V DSAT  S×V DSAT W   S×W C ox   C ox /S I d   S×I d

20. Penn ESE370 Fall2014 -- DeHon 20 Gate Delay  Gate Delay scaling?   gd =Q/I=(CV)/I  V   S×V  I d   S×I d  C   S×C   gd   S×  gd Note: Ids as current source V is changing

21. 21 Overall Scaling Results, Transistor Speed and Leakage. Preliminary Data from 2005 ITRS. Intrinsic Transistor Delay,  CV/I (lower delay = higher speed) Leakage Current (HP: standby power dissipation issues) HP  Target: 17%/yr, historical rate LOP LSTP LSTP  Target: Isd,leak ~ 10 pA/um LOP HP HP = High-Performance Logic LOP = Low Operating Power Logic LSTP = Low Standby Power Logic 17%/yr rate Planar Bulk MOSFETs Advanced MOSFETs

22. Penn ESE370 Fall2014 -- DeHon 22 Wire Delay  Wire delay scaling?   wire =R  C  R   R/S  C   S×C   wire   wire …assuming (logical) wire lengths remain constant... Important cost shift we will have to watch

23. Penn ESE370 Fall2014 -- DeHon 23 Power Dissipation (Dynamic) Capacitive (Dis)charging scaling?  P=(1/2)CV 2 f  V   S×V  C   S×C  P   S 3 ×P Increase Frequency?   gd   S×  gd  So: f   f/S ?  P   S 2 ×P

24. Penn ESE370 Fall2014 -- DeHon 24 Effects? Area S 2 Capacitance S Resistance 1/S Threshold (V th ) S Current (I d ) S Gate Delay (  gd ) S Wire Delay (  wire ) 1 Power S 2  S 3

25. Penn ESE370 Fall2014 -- DeHon 25 Power Density P   S 2 P (increase frequency) P   S 3 P  (dynamic, same freq.) A   S 2 A Power Density: P/A two cases? –P/A   P/A increase freq. –P/A   S×P/A same freq.

26. Penn ESE370 Fall2014 -- DeHon 26 Cheating… Don’t like some of the implications –High resistance wires –Higher capacitance –Atomic-scale dimensions …. Quantum tunneling –Need for more wiring –Not scale speed fast enough

27. Penn ESE370 Fall2014 -- DeHon 27 Improving Resistance R=  L/(W×t) W   S×W L, t similar R   R/S  What might we do?  Don’t scale t quite as fast  now taller than wide.  Decrease  (copper) – introduced 1997 http://www.ibm.com/ibm100/us/en/icons/copperchip/

28. Penn ESE370 Fall2014 -- DeHon 28

29. Penn ESE370 Fall2014 -- DeHon 29 Capacitance and Leakage Capacitance per unit area –C ox =  SiO 2 /T ox –T ox   S×T ox –C ox   C ox /S What’s wrong with Tox = 1.2nm? source: Borkar/Micro 2004

30. Penn ESE370 Fall2014 -- DeHon 30 Capacitance and Leakage Capacitance per unit area –C ox =  SiO 2 /T ox –T ox   S×T ox –C ox   C ox /S Reduce Dielectric Constant  (interconnect) and Increase Dielectric to substitute for scaling T ox (gate quantum tunneling) What might we do?

31. ITRS 2009 Table PIDS3B Low Operating Power Technology Requirements Grey cells delineate one of two time periods: either before initial production ramp has started for ultra-thin body fully depleted (UTB FD) SOI or multi-gate (MG) MOSFETs, or beyond when planar bulk or UTB FD MOSFETs have reached the limits of practical scaling (see the text and the table notes for further discussion). Year of Production2009201020112012201320142015201620172018201920202021202220232024 MPU/ASIC Metal 1 (M1) ½ Pitch (nm) (contacted) 5445383227242118.916.91513.411.910.69.58.47.5 Lg: Physical Lgate for High Performance logic (nm) 2927242220181715.31412.811.710.79.78.98.17.4 L g : Physical Lgate for Low OperatingPower (LOP) logic (nm) [1]3229272422181715.31412.811.710.79.78.98.17.4 EOT: Equivalent Oxide Thickness (nm) [2] Extended planar bulk 10.9 0.850.8 UTB FD 0.90.850.80.750.7 MG 0.8 0.750.730.7 0.65 0.6 Gate poly depletion (nm) [3] Bulk 0.27 00000000000000 Channel doping (E18 /cm3) [4] Extended Planar Bulk 33.74.555.50.1 Junction depth or body Thickness (nm) [5] Extended Planar Bulk (junction) 141311.5109 UTB FD (body) 76.265.14.7 MG (body) 87.676.45.85.44.84.44.24 EOT elec : Electrical Equivalent Oxide Thickness (nm) [6] Extended Planar Bulk 1.641.531.231.181.14 UTB FD 1.31.251.21.151.1 MG 1.2 1.151.131.1 1.05 11 Penn ESE370 Fall2014 -- DeHon 31

32. Penn ESE370 Fall2014 -- DeHon 32 High-K dielectric Survey Wong/IBM J. of R&D, V46N2/3P133—168, 2002

33. Penn ESE370 Fall2014 -- DeHon 33 Intel NYT Announcement Intel Says Chips Will Run Faster, Using Less Power –NYT 1/27/07, John Markov –Claim: “most significant change in the materials used to manufacture silicon chips since Intel pioneered the modern integrated- circuit transistor more than four decades ago” –“Intel’s advance was in part in finding a new insulator composed of an alloy of hafnium…will replace the use of silicon dioxide.”

34. Penn ESE370 Fall2014 -- DeHon 34 Wire Layers = More Wiring

35. Penn ESE370 Fall2014 -- DeHon 35 [ITRS2005 Interconnect Chapter] Typical chip cross-section illustrating hierarchical scaling methodology

36. Penn ESE370 Fall2014 -- DeHon 36 Improving Gate Delay   gd =Q/I=(CV)/I  V   S×V  I d =(  C OX /2)(W/L)(V gs -V TH ) 2  I d   S×I d  C   S×C   gd   S×  gd  Lower C.  Don’t scale V. Don’t scale V: V  V I  I/S  gd  S 2 ×  gd How might we accelerate?

37. Penn ESE370 Fall2014 -- DeHon 37 …But Power Dissipation (Dynamic) Capacitive (Dis)charging  P=(1/2)CV 2 f  V   V  C   S×C Increase Frequency?  f   f/S 2 ?  P   P  S If not scale V, power dissipation not scale down.

38. Penn ESE370 Fall2014 -- DeHon 38 …And Power Density P   P/S (increase frequency) But…    S 2 ×  What happens to power density? P/A   (1/S 3 )P Power Density Increases …this is where some companies have gotten into trouble…

39. Historical Voltage Scaling Frequency impact? Power Density impact? Penn ESE370 Fall2014 -- DeHon 39 http://software.intel.com/en-us/articles/gigascale-integration-challenges-and-opportunities/

40. Penn ESE370 Fall2014 -- DeHon 40 Scale V separately from S   gd =Q/I=(CV)/I  V  I d =(  C OX /2)(W/L)(V gs -V TH ) 2  I d   V 2 /S×I d  C   S×C   gd   SV/(V 2 /S))×  gd   gd   S 2 /V)×  gd Ideal scale: S=1/100 V=1/100  =1/100 F ideal =100 Cheating: S=1/100 V=1/10  =1/1000 F cheat =1000 f cheat /f ideal =10

41. Power Density Impact P=1/2CV 2 f P~= S V 2 (V/S 2 ) = V 3 /S P/A = (V 3 /S) / S 2 = V 3 /S 3 V=1/10 S=1/100 P/A  1000 (P/A) Penn ESE370 Fall2014 -- DeHon 41

42. uProc Clock Frequency Penn ESE370 Fall2014 -- DeHon 42 The Future of Computing Performance: Game Over or Next Level? National Academy Press, 2011 http://www.nap.edu/catalog.php?record_id=12980 MHz

43. uP Power Density Penn ESE370 Fall2014 -- DeHon 43 The Future of Computing Performance: Game Over or Next Level? National Academy Press, 2011 http://www.nap.edu/catalog.php?record_id=12980 Watts

44. Penn ESE370 Fall2014 -- DeHon 44 What Is A “Red Brick” ? Red Brick = ITRS Technology Requirement with no known solution Alternate definition: Red Brick = something that REQUIRES billions of dollars in R&D investment [from Andrew Kahng]

45. Penn ESE370 Fall2014 -- DeHon 45 The “Red Brick Wall” - 2001 ITRS vs 1999 Source: Semiconductor International - http://www.e-insite.net/semiconductor/index.asp?layout=article&articleId=CA187876 [from Andrew Kahng]

46. ITRS 2009 Year of Production2009201020112012201320142015201620172018201920202021202220232024 MPU/ASIC Metal 1 (M1) ½ Pitch (nm) (contacted) 5445383227242118.916.91513.411.910.69.58.47.5 Lg: Physical Lgate for High Performance logic (nm) 2927242220181715.31412.811.710.79.78.98.17.4 L g : Physical Lgate for Low OperatingPower (LOP) logic (nm) [1]3229272422181715.31412.811.710.79.78.98.17.4 EOT: Equivalent Oxide Thickness (nm) [2] Extended planar bulk 10.9 0.850.8 UTB FD 0.90.850.80.750.7 MG 0.8 0.750.730.7 0.65 0.6 Gate poly depletion (nm) [3] Bulk 0.27 00000000000000 Channel doping (E18 /cm3) [4] Extended Planar Bulk 33.74.555.50.1 Junction depth or body Thickness (nm) [5] Extended Planar Bulk (junction) 141311.5109 UTB FD (body) 76.265.14.7 MG (body) 87.676.45.85.44.84.44.24 EOT elec : Electrical Equivalent Oxide Thickness (nm) [6] Extended Planar Bulk 1.641.531.231.181.14 UTB FD 1.31.251.21.151.1 MG 1.2 1.151.131.1 1.05 11 C g ideal (fF/  m) [7] Extended Planar Bulk 0.670.6550.7440.7080.669 UTB FD 0.5870.5080.4830.460.439 MG 0.4830.4410.420.390.3660.3340.320.2920.280.255 J g,limit : Maximum gate leakage current density (A/cm 2 ) [8] Extended Planar Bulk 8695100110140 UTB FD 140150170180200 MG 170180200220230260280310280310 V dd : Power Supply Voltage (V) [9] Bulk/UTB FD/MG 0.95 0.85 0.8 0.75 0.7 0.65 0.6 V t,sat : Saturation Threshold Voltage (mV) [10] Extended Planar Bulk 428436407419421 UTB FD 311317320323327 MG 288294297299 297300304311316 I sd,leak (nA/  m) [11] Bulk/UTB FD/MG 5555555555555555 Mobility enhancement factor due to strain [12] Bulk/UTB FD/MG 1.8 Effective Ballistic Enhancement Factor, Kbal [13] Bulk/UTB FD/MG 11111.061.121.191.261.341.421.51.591.691.791.92.01 R sd : Effective Parasitic series source/drain resistance (Ω-µm) [14] Extended Planar Bulk 220200170160150 UTB FD 170165160150 MG 160 150 140 130 I d,sat : NMOS Drive Current with series resistance (µA/µm) [15] Extended Planar Bulk 700746769798729 UTB FD 9049999841,0801,050 MG 1,0701,1201,1001,1901,1301,2101,1401,2001,3201,370 C g fringing capacitance (fF/  m) [16] Extended Planar Bulk 0.2430.2380.2520.2320.239 UTB FD 0.1670.1590.1760.1690.17 MG 0.1860.1790.180.181 0.1820.1790.180.1790.18 C g,total : Total gate capacitance for calculation of CV/I (fF/µm) [17] Extended Planar Bulk 0.9130.8930.9960.940.908 UTB FD 0.750.670.660.630.61 MG 0.6690.620.60.5710.5470.5160.4990.4720.4590.435 τ =CV/I: NMOSFET intrinsic delay (ps) [18] Extended Planar Bulk 1.241.141.111 UTB FD 0.670.530.50.430.4 MG 0.470.410.380.330.310.280.260.230.210.19 Penn ESE370 Fall2014 -- DeHon 46

47. Penn ESE370 Fall2014 -- DeHon 47 Conventional Scaling Ends in your lifetime Perhaps already: –"Basically, this is the end of scaling.” May 2005, Bernard Meyerson, V.P. and chief technologist for IBM's systems and technology group

48. Penn ESE370 Fall2014 -- DeHon 48 Big Ideas [MSB Ideas] Moderately predictable VLSI Scaling –unprecedented capacities/capability growth for engineered systems –change –be prepared to exploit –account for in comparing across time –…but not for much longer

49. Penn ESE370 Fall2014 -- DeHon 49 Admin HW5 –Regions –Hardest yet –…hope you’ve started –Due Tuesday