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Published byStewart Austin Modified over 9 years ago
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The Abstract simulator
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Simulator/Simulation Concepts n Simulator: responsible for executing a model’s dynamics (resented as instructions) in a given formalism. n Abstract simulator: a characterization of what needs to be done in executing a model’s instructions –atomic simulator –coupled simulator n Simulation engines: enforce particular realizations of abstract simulator n Simulations can be executed as: –Sequential –Parallel –Distributed (sequential/parallel) –Real-Time
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–Simulation performance : event list management event list: insert, delete, location search time: not constant (solution : priority queue implementation heap) TimeEvent routine t1t1 E1E1 :: Transition: event generation until event list empty Standard DES mechanisms
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(i) Concept : separation of control (scheduling) algorithm from data(model) ABC AB C AB User’s spec C:ABC C:AB S:C S:AS:B System’s simulation algorithm request Ack Passive agent (data) server Active agent (control) client S : C : simulator for model C (simulation algorithm) C: AB : Coordinator for model AB (simulation algorithm) (ii) Hierarchical scheduling No global event list Abstract simulation : Hierarchical simulation (scheduling) algorithm
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(iii) Two classes of simulations simulator class Associated with atomic DEVS ( int, ext, ta, ) invoke coordinator class Associated with coupled DEVS Event routing Hierarchical scheduling GENBUFFERPROC out in out done Processors: two types of simulation entities
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Simulation entities example
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Message passing External Events Internal Events
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C: GENBUFPROC GENBUFPROC C: BUFPROC BUFPROC S : GEN GEN S : PROC PROC S : BUF BUF (x, t) : external input event arrival at time t (*, t) : internally-generated event at time t that notifies the scheduled time is completely elapsed (done, t N ) : synchronization event generated at time t N that notifies the next scheduled time is t N (x, t) (*, t) (done, t N ) (x, t) (*, t) (x, t) (*, t) (x, t) (*, t) Types of messages involved and their interaction
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Simulator for AM (x, t) (*, t) (done, t N ) When receive (x,t), invoke ext and ta setting When receive (*,t), invoke int, and ta setting Wait M: ext M: M: int ta (x, t)(*, t) (done, t N ) Coordinator for CM (x, t) (*, t) (done, t N ) Wait Route (x,t) wait till done Route(*,t) imminent(i*) component schedule (x, t) (*, t) (done, t N ) Wait i* done and (x,t) from i* done Minimum t N SELECT needed Simulator and Coordinator activities
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Coordinator (x, t) (*, t) (done, t N ) tNtN tLtL Wait Route (x,t) wait till done Route(*,t) imminent(i*) component schedule (x, t) (*, t) (done, t N ) Wait i* done and (x,t) from i* done When receive (x,t) if t L t t N then send (x,t) to connected component(s) wait all component(s) done t L := t t N := min{t Ni | i: component} send (done, t N ) to upper level coordinator else error When receive (*,t) if t = t N then find component(s) with t N select one i* send (*,t) to i* wait response: (y i, port) translate y i* to x send x to its influencees wait i* and its influencees done t L := t t N := min{t Ni | i: i* + its influencees } send (done, t N ) to upper level coordinator else error Coordinator activities
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GEN BUF PROC out in done 12345678 GEN ta(BUF) : 2 1 3 2 1 ta(PROC) : 1 2 1 3 2 Root C : G+B+P C : B+P S : BS : P S : G BUF+PROC GEN+BUF+PROC G BP B G B P G P SELECT Coordinator: example
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S : GENS : BUFS : PROCC : B+PC : G+B+PROOT t (done, t N =1)0 1 2 3 3 2 1 (*, 1) (s) int (s) (6) ext (s) (5) Route: (4) Route: ta = 1 ta = 2 S:BUF C:B+P schedulet N =2t N =3 t = 1 (done, 2) 1 2 3 (*, 2) 3 2 1 (s) int (s) ext (s) ta = 2 ta = 1 t = 2 schedulet N =4t N =3 (done, 3) 1 2 3 3 2 1 (S) int (s) ext (s) ta = 1 ta =1 schedulet N =4 (done, 4) 1 2 3 t N =4 t = 3(*, 3) t = 4 3 2 1 (s) int (s) ext (s) ta = 2 (*, 4) schedulet N =4 (done, 4) 1 2 3 t N =6 Coordinator: example (contd.) t N =3
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1. Modeler has no responsibility in time control No worry about execution sequence (No explicit initial state) 2. Separation of characteristic functions in modeling simplicity, reusability 3. Close under coupling operation BUF FIFO (First-in, First-out) LIFO (Last-in, First-out) insert delete insert delete FIFOLIFO Example of 2 : Buffer ext : X Q S int : S S : S Y ta : S R + 0, reusable Note on abstract simulator
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Mensaje I / 00:00:00:000 / Root(00) para top(01) Mensaje I / 00:00:00:000 / top(01) para gen(02) Mensaje D / 00:00:00:000 / gen(02) / 00:00:00:000 para top(01) Mensaje D / 00:00:00:000 / top(01) / 00:00:00:000 para Root(00) Mensaje * / 00:00:00:000 / Root(00) para top(01) Mensaje * / 00:00:00:000 / top(01) para gen(02) Mensaje Y / 00:00:00:000 / gen(02) / out / 0.000 para top(01) Mensaje D / 00:00:00:000 / gen(02) / 00:00:03:324 para top(01) Mensaje Y / 00:00:00:000 / top(01) / out / 0.000 para Root(00) Mensaje D / 00:00:00:000 / top(01) / 00:00:03:324 para Root(00) Mensaje * / 00:00:03:324 / Root(00) para top(01) Mensaje * / 00:00:03:324 / top(01) para gen(02) Mensaje Y / 00:00:03:324 / gen(02) / out / 1.000 para top(01) Mensaje D / 00:00:03:324 / gen(02) / 00:00:02:308 para top(01) Mensaje Y / 00:00:03:324 / top(01) / out / 1.000 para Root(00) Mensaje D / 00:00:03:324 / top(01) / 00:00:02:308 para Root(00) Mensaje * / 00:00:05:632 / Root(00) para top(01) Generator CD++ - Simulation
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