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2/27/2016 1 VLSI Physical Design Automation Prof. David Pan Office: ACES 5.434 Detailed Routing (II)

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Presentation on theme: "2/27/2016 1 VLSI Physical Design Automation Prof. David Pan Office: ACES 5.434 Detailed Routing (II)"— Presentation transcript:

1 2/27/2016 1 VLSI Physical Design Automation Prof. David Pan dpan@ece.utexas.edu Office: ACES 5.434 Detailed Routing (II)

2 2 2/27/2016 Yoshimura and Kuh’s Method Source: “Efficient Algorithms for Channel Routing” by T. Yoshimura and E. Kuh IEEE Trans. On Computer-Aided Design of Integrated Circuits and Systems. Vol. CAD-1, pp25-35, Jan 1982

3 3 2/27/2016 Characterizing Channel Routing Problem 1 3 5 8 9 2 6 7 104 1 3 5 4 8 9 7 6 2 Vertical constraint graph G v Horizontal constraint graph 0 1 4 5 1 6 7 0 4 9 10 10 2 3 5 3 5 2 6 8 9 8 7 9 2 1 5 4 3 6 7 8 9 10

4 4 2/27/2016 Zone Representation 01451670491010 235352689879 2 1231234512345 12452464674784789 7897910 910 12345Zone: Remarks: A new zone appears when some intervals begin after some intervals end. intervals begin after some intervals end.

5 5 2/27/2016 Zone Representation 2 1231234512345 12452464674784789 7897910 910 1 2 3 4 5 6 7 8 9 10 12345Zone:

6 6 2/27/2016 Merging of Nets 14 5 3 9 8 10 7 6 2 1 2 3 4 5 6 7 8 9 10 1 4 5,6 3 9 8107 2 1 2 3 4 5,6 7 8 9 10

7 7 2/27/2016 Scanning the Zones 1 2 3 4 5 6 7 8 9 10 Left = {1, 3, 5} Right = {6} 1 2 3 4 5,6 7 8 9 10 Left = {1, 2, 3} Right = {7} 1,7 2 3 4 8 9 10 Left = {2, 3, 5.6} Right = {8, 9} 5,6

8 8 2/27/2016 Scanning of Zones 1,7 2 3,8 4 10 Left = {2, 3.8, 4} Right = {10} 5,6,9 1,7 2 3,8 4,10 5,6,9

9 9 2/27/2016 Merging VCG14 5 3 9 8 10 7 6 2 1 4 5,6 3 9 8107 2 1,7 4,10 5,6,9 3,8 2 1,7 4 5,6,9 3,8 10 2 1,7 4 5,6 3 9 8 10 2

10 10 2/27/2016 Assigning Tracks 1,7 4,10 5,6,9 3,8 2 Track 1 Track 2 Track 3 Track 4 (or 5) Track 5 (or 4)

11 11 2/27/2016 Merging of Nets Make sure that the VCG remains acyclic There are two approaches: –First approach: Merge the pairs sequentially. Select pairs to minimize the increase in the length of the longest path in the VCG. –Second approach: Merge all pairs simultaneously. Select pairs to maximize the total no. of matches. We will focus on the second approach: “ simultaneous merging ”.

12 12 2/27/2016 Shortcomings of the First Approach Observation: Merging of two nodes may block subsequent merging Net f cannot be merged with either c or g. But, if we merged a with d, c with e then f can be merged with net b a b c g h 4 d e k f 321 a.d b.e c g h 4 k f 321 a g c e b k h f d a.d gc b.e k h f

13 13 2/27/2016 Processing Zone a b c g hd e k f a g c e b k h f d Processing Zone 1 Bipartite graph LEFT={a,b,c} RIGHT={d,e} a b c d e Delay merging!!(Both d and e do not terminate at zone 2 Processing Zone 2 a b c d e f g a b c d e f g Modify matching Cyclic conflict!! Merge a&d, b&f, delay merging c&e LEFT={a.d, b.f,c,g} RIGHT={h,k,e} Merge two nets when both of them terminate!

14 14 2/27/2016 Simultaneous Merging Use the maximum cardinality matching in bipartite graph: 1 2 3 4 5 6 7 8 9 10 Left = {1, 3, 5} Right = {6} 1 36 5 Find the maximum matching in this bipartite graph such that the resultant VCG is still acyclic.

15 15 2/27/2016 Cyclic Conflicts Simultaneous merging can produce cyclic conflicts: 2 1 3 4 2 14 3 1 2 3 4 Bipartite graph, G VCG 2 14 3 1,3 2,4 Cyclic!

16 16 2/27/2016 Cyclic Conflicts Bipartite graph G(V,E) Algorithm AA A set of edges E’ Theorem: Any matching in G(V,E-E’) is feasible.

17 17 2/27/2016 An Example of Algorithm AA a b c d g h i g b c a d i h N = set of nodes that have in-degree 0 g b c a i h a b c d g h i isolated Remove edges between vertices in N

18 18 2/27/2016 An Example of Algorithm AA a b c g h i g b c a i hab cgh i g b c i h No isolated node. Then select among N the node with the smallest degree in the bipartite graph. Remove and put its edges to E’. N b c g h i aisolated

19 19 2/27/2016 An Example of Algorithm AA b c g h i g b c i h N b hgc i isolated b c i hN c i bhisolated bc h

20 20 2/27/2016 An Example of Algorithm AA c bh At the end, all edges are removed, and E’ = {(a,h)} Since E’  , according to the corollary, any matching in the bipartite graph G(V, E-E’) is feasible. We will find a matching in G(V, E-E’) c b h bc h N Why does it work?

21 21 2/27/2016 Comments ¬Avoid unnecessary introduction of dogleg, use a process “merging of subnets” subnet i and subnet j can be merged  merging subnet i and subnet j will not increase the longest path length passing through H ­Reduce CPU time by: # of edges/nodes in the bipartite graph is limited by a parameter(e.g. =3 in the program) ®Need not start at zone 1 In general, can obtain better results by starting at the max density zone Max density zone

22 22 2/27/2016 Routing Examples by Y-K’s Algorithm number of tracks=18 maximum density =18 number of tracks=17 maximum density =17 Example 3c Example 4b

23 23 2/27/2016 Routing Examples by Y-K’s Algorithm (Cont’d) number of tracks=20 maximum density =20 number of tracks=28 maximum density =19 Example 5 Deutsch’s Difficult example without dogleg

24 24 2/27/2016 Deutsch’s Difficult Example # columns =174, # nets=72 density=19 Deutsch’s difficult example with doglegs number of tracks=20 maximum density=19

25 25 2/27/2016 Summary of Yoshimura and Kuh’s Algorithm aSplit multi-terminal nets into 2-terminal subnets aMerging subnets to share tracks aConsider both HCG and VCG aGlobal matching and delayed merging help Shortcomings aCannot produce unrestricted doglegs aVCG cannot have cycle

26 26 2/27/2016 Greedy Channel Router R.L. Rivest and C.M. Fiduccia “ A Greedy Channel Router”, 19th DAC, 1982 P418-424 aA simple linear time algorithm aGuarantee the completion of all the nets (may extend to right-hand side of the channel) aProduce both restricted doglegs and unrestricted doglegs

27 27 2/27/2016 Left-to-right, Column-by-column scan c:=0; while (not done) do begin c:=c+1; complete wiring at column c; end; In general, a net may be (1) empty (net 5) (2) unsplit (nets 1,4) (3) split (net 3) (4) completed (net2) Overview of Greedy Router 1 3 1 2 1 5 2 1 2 3 4 5 4 4 1 3 4 3

28 28 2/27/2016 Operations at Each Column At each column, the greedy router tries to maximize the utility of the wiring produced: A: Make minimal feasible top/bottom connections; B: Collapse split nets; C: Move split nets closer to one another; D: Raise rising nets/lower falling nets; E: Widen channel when necessary; F: Extend to next column; 1 3 1 2 1 5 2 1 2 3 4 5 4 4

29 29 2/27/2016 (A) Make Minimal Feasible Top/Bottom Connections 234234 234234 44 11 231231 231231 00 11 A A* B B* 2121 2323 22 11 C C* 12341234 5 0 D D* 12341234 5 0 12341234 5 5 F F* 12341234 5 5 32143214 3 2 E E* 32143214 3 2

30 30 2/27/2016 ( B ) Collapse Split Nets 0 2 132132 0 2 132132 G G* 0 0 1341413414 0 H H* 0 1341413414 0 1 212343212343 I I* 0 1 212343212343 0 0 12121212 0 12121212 J J* 0

31 31 2/27/2016 ( C ) Move Split Nets Closer 0 0 12121212 k k* 0 0 12121212

32 32 2/27/2016 ( D ) Rising/Falling L L* 0 1 3434 falling rising 0 1 3434 falling rising

33 33 2/27/2016 M M* 7 0 15161516 ( E ) Insert New Track 7 0 15161516

34 34 2/27/2016 7 0 15161516 ( F ) Extend to Next Column 7 N

35 35 2/27/2016 Comments on Greedy Router (Rivest&Fiduccia 1982) aAlways succeed (even if cyclic conflict is present); aAllows unrestricted dogleg; aAllows a net to occupy more than 1 track at a given column; aMay use a few columns off the edge; 1 3 1 2 1 5 2 1 3 3 4 5 4 4 A column off the edge Unrestricted dogleg Net 1 occupies two tracks at this column; it also “ wraps-around

36 36 2/27/2016 Parameters to Greedy Router aInitial-channel-width icw aMinimum-jog-length mjl aSteady-net-constant snc aUsually start icw as d. the density aMjl controls the number of vias, use a large mjl for fewer vias aSnc also controls # of vias, typical value=10

37 37 2/27/2016 Experimental Results aRuns very fast a20-track solution to the Deutsch’s Difficult Example


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