1. ECE 171 Digital Circuits Chapter 9 Hazards Herbert G. Mayer, PSU Status 2/21/2016 Copied with Permission from prof. Mark Faust @ PSU ECE

2. Syllabus Glitches and Hazards Static Logic Hazards Static Function Hazards Dynamic Hazards Decoders Multiplexers References

3. Glitches and Hazards So far we assumed: steady state of a circuit Steady state is equivalent to having “waited” a long time for signals to settle Long time meaning: more than a cycle for clocked, or longer than signal propagation time for un-clocked In practice, the actual time for a signal to propagate to the output gate can be long, and the signal may depend on which path that signal has taken Depending on such paths, outputs may experience an unintended pulse, AKA glitch Glitch means: though the steady state produces the correct signal, an opposite signal occurs momentarily

4. Glitches and Hazards Hazard means the condition for a glitch exists It doesn’t mean the hazard actually occurs each time It doesn’t even mean the hazard occurs at all during this execution It means, the hazard can occur, based on input signal combinations, on actual signal path taken The circuit designer must identify are acceptable or not If hazards are not acceptable, the designed must analyze and take design steps to avoid them; e.g. via consensus terms

5. Glitches and Hazards Glitch: Wrong signal in a circuit due to unequal delay paths; this is the manifestation of a hazard Function Hazard: May cause glitch when two or more inputs change at once. Cannot generally be removed by adding logic. Logic Hazard: Is a glitch when one input changes. Can be removed by adding logic: AKA consensus terms Dynamic Hazard: Occurs when output of the circuit changes unexpectedly more than once for a single input change. Static Hazard: Occurs when output of the circuit is supposed to be constant. There are 2 kinds: unexpected 0 or unexpected 1 Function and Logic Hazards can be Static or Dynamic. 5

6. Glitches and Hazards Definition: A static-1 hazard is an unexpected 0 output, generated by a pair of input combinations such that: a.) the two inputs differ by just 1 variable, b.) both combinations produce a 1 output signal, yet c.) an unwanted 0 signal occurs during the single input transition Definition: A static-0 hazard is an unexpected 1 output, generated by a pair of input combinations such that: a.) the two inputs differ by just 1 variable, b.) both combinations produce a 0 output signal, yet c.) an unwanted 1 signal occurs during the single input transition Definition: A dynamic hazard is the possibility of an unexpected change of the output signal more than once as a result of a single input signal change

7. Static Logic Hazards Single input changed. Resulting output should have remained constant: 1 in case(a). 0 in case(b). However, a glitch appeared before the output settled back to its correct level Two-level SOP circuits may see static-1 hazards Two-level POS circuits may see static-0 hazards 7

8. Static-1 Hazard with SoP

9. Static-1 Logic Hazard Students draw minimized circuit in class, SOP form: And- and Or-gates OK, better even Nand-gates 9

10. Static-1 Logic Hazard Consider inputs ABC 111 time t 1 110 time t 2 1 1 1 NAND/NAND Implementation 1 1 0 10

11. Observe Carefully: If first input at time t 1 is: A B C = 1 1 1, the output F1 will be 1, due to nand-gate with inputs B C Then at time t 2 the input changes to A B C = 1 1 0 Output F1 again is 1, due to nand-gate with inputs A C’, but the length (and thus the length of time) for the input path with signal C’ is longer, due to the inverter; may be critical! In some instances that may be a sufficient delay to create a brief static 1 hazard, AKA 0 glitch 1 hazard alluding to: signal should be 1 but isn’t Static alluding to: signal should be 1 before, should be 1 after, but there is a different value; must be 0

12. Static-1 Logic Hazard Consider inputs ABC 111 110 1 1 1 NAND/NAND Implementation 1 1 0 12

13. Detect, Eliminate Static-1 Hazard 13

14. To avoid this type of hazard: With input transition 111 -> 110, output signal F1 should stay 1: was 1 initially, should remain 1 Yet the “second 1” may arrive just a bit late: longer path Add 3 rd signal path (consensus term) that covers areas of 1s with further option to generate 1 signal: AB Countermeasure

15. Detect, Eliminate Static-1 Hazard 15

16. Static-0 Hazard with SoP

17. Static-0 Hazard Implement a hazard-free circuit for the 0s of the previous function using NOR gates SoP Form for 0s: 17 Students write F1( A, B, C ) in SoP form, for 0s F1 =... Students!!

18. Static-0 Hazard Implement a hazard-free circuit for the 0s of the previous function using NOR gates SOP Form for 0s: 18 Hazard occurs at boundary of 2 terms, both of which deliver the same signal of interest, 0 here, at different times Consensus term needed to deliver same signal, 0 here, if the other 2 terms may not “agree” about timing To avoid a logic 1 glitch

19. Static-0 Hazard Where is the critical boundary? Look for: products grouped together! Look for: adjacent (neighboring) terms in K-map Add new term covering both, adjacent terms Is redundant for signal-generation, but adds needed value that otherwise might get lost, due to glitch

20. Static-0 Hazard Students, which term is to be added? One that covers 0s, when 2 neighboring terms should be 0, but happen to become non-zero! Without adding new 0 terms! I.e. covering existing neighboring zeros! And that is... Which term?

21. Static-0 Hazard Implement a hazard-free circuit for the 0s of the previous function using NOR gates SOP Form for 0s Needed Cover Term Included 21

22. Static Function Hazards Result of multiple input signals changing Cannot generally be removed by adding logic Unless we design new logic! 22

23. Hazard Example

24. Given the K-Map for function Haz() below: Write function Haz() in SoP form Identify where hazards can occur Devise a hazard-free function Haz’() equivalent to Haz() 24

25. Hazard Example Assuming Haz() = a c’ + a’ c The hazard arises between cells: a b c’ d and a b c d Add new term a b d, so: Haz’() = a c’ + a’ c + a b d 25

26. Dynamic Hazard

27. Dynamic Hazards Generally occur in multi-level circuits with multiples paths, having different delays from input to output Do not occur in 2-level SOP (or POS) implementations Requires these further levels, creating more choices, each with differing timings 27

28. Implementations for Complex Functions and Their Delays 28

29. Decoders & Dmuxes

30. Decoders n-to-2 n decoder Converts binary code on n=2 input lines to one of 2 n =4 output lines Students design circuit in class now, ignore EN 30 When decoder has EN (enable) input, it referred to as demultiplexer (dmux). EN is often active low.

31. Decoders Converts binary code on n input lines to one of 2 n output lines I1I0 Y0 Y1 Y2 Y3 31

32. Decoders Converts binary code on n input lines to one of 2 n output lines Now with EN signal: I1I0 Y0 Y1 Y2 Y3 EN 32

33. Decoders B 1 B 0 F 0 F 1 F 2 F 3 0 0 0 1 1 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 0 Sometimes outputs are active low too! 33 F0 F1 F2 F3

34. Decoders When using decoders with active low outputs use “bubble matching” to use correct gate Example: Implement XNOR with DMUX 34

35. Multiplexers (Data Selectors) Mux Directs one of 2 n inputs to a single output S 0 D 1 D 0 F 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 0 1 1 0 1 1 1 1 1 S 0 F 0 D 0 1 D 1 35

36. Multiplexers Sometimes include Enable input EN S 0 F 0 0 D 0 0 1 D 1 1 X 0 Effective as universal function generator 36

37. Type 0 Universal Function Implementation with a Mux Uses the function inputs (X,Y,Z) to “select” the value of the function by selecting the minterm corresponding to the inputs. If the minterm m i is in the function the corresponding D i input is tied to 1 (0 otherwise) 37

38. Type 1 Universal Function Implementation with a Mux 38

39. A word about “optimization” What are we optimizing? –Variables (inputs – connectors) –Terms (gates, interconnect) –Unique fan-in (IC packages – same number of gates) –Number of logic levels (speed) –NAND/NOR Implementations (speed, IC packages,…) –Complexity (Design time – time to market) –Design Time & Flexibility/Cost (FPGA vs. ASIC) 39