1. -Dinesh Somasekhar, Shih-Lien Lu, Bradley Bloechel, Greg Dermer, Konrad Lai, Shekhar Borkar and Vivek De Solid-State Circuits Conference, 2005. ESSCIRC 2005. Proceedings of the 31st European 12-16 Sept. 2005 Page(s):355 - 358 Digital Object Identifier 10.1109/ESSCIR.2005.1541633Solid-State Circuits Conference, 2005. ESSCIRC 2005. Proceedings of the 31st European

2. A 10Mbit, 15GBytes/sec Bandwidth 1T- DRAM Chip Characteristics Technology 150nm 6 Metal Logic Process Cell Area 1.08 um2 Die Size 6mm x 8mm 1Mbit Array Size 1mm x 2.3mm Array Efficiency 52% Array Density 42.7 Mbit/cm2 Comparable SRAM Density 15 Mbit/cm2 DRAM/SRAM Density 2.85 X Retention Time 100us Percentage of Failing Bits 0.035 %

3. A 10Mbit, 15GBytes/sec Bandwidth 1T- DRAM Chip Characteristics Power Supply 1.5V Word Line material PolySilicon Storage Cell Capacitance 5 fF Bit Line Swing 25mV - 50mV Bit Line Bias -100 mV Worst case refresh time 100us Maximum cells per row 512 Error Correcting column redundancy Number of banks 10x32 External I/O width 128bit

4. A 10Mbit, 15GBytes/sec Bandwidth 1T- DRAM Chip Characteristics Inadequate bit line swing Residual offset in LSA Problems

5. Any Questions ?