1. 1 Monolithic CMOS Detectors for Tracking and the Sticky Photo-Gate Wieman RNC LBNL 9-Feb-2005

2. 2 Things to cover  Brief report on the STAR Heavy Flavor Tracker program, an inner vertex detector to use monolithic CMOS pixel detectors  Some work on a photo-gate, an attempted improvement on the CMOS pixels

3. 3 A Heavy Flavor Tracker for STAR Z. Xu Brookhaven National Laboratory, Upton, New York 11973 Y. Chen, S. Kleinfelder, A. Koohi, S. Li University of California, Irvine, California H. Huang, A. Tai University of California, Los Angeles, California 90095 V. Kushpil, M. Sumbera Nuclear Physics Institute AS CR, 250 68 Rez/Prague, Czech Republic C. Colledani, W. Dulinski, A. Himmi, C. Hu, A. Shabetai, M. Szelezniak, I. Valin, M. Winter Institut de Recherches Subatomique, Strasbourg, France M. Miller, B. Surrow, G. Van Nieuwenhuizen Massachusetts Institute of Technology, Cambridge, MA 02139 F. Bieser, R. Gareus, L. Greiner, F. Lesser, H.S. Matis, M. Oldenburg, H.G. Ritter, L. Pierpoint, F. Retiere, A. Rose, K. Schweda, E. Sichtermann, J.H. Thomas, H. Wieman, E. Yamamoto Lawrence Berkeley National Laboratory, Berkeley, California 94720 I. Kotov Ohio State University, Columbus, Ohio 43210 (The contributing authors to this proposal, listed above, gratefully acknowledge the support of their funding agencies.) Cover page from proposal just submited to STAR managment

4. 4 STAR Micro Vertex Detector  Two layers u1.5 cm radius u4.5 cm radius  24 ladders u2 cm X 20 cm each u< 0.3% X 0 u~ 100 Mega Pixels Purpose: Greatly improve D meson capability in STAR

5. 5 Selected Detector Parameters and Specifications Min I efficiency98% Accidental rate< 100 /cm 2 Position resolution< 10  m Number of pixels98,304,00 Pixel dimension30  m  30  m Detector chip active area19.2 mm  19.2 mm Detector chip pixel array640  640 Number of ladders24 Ladder active area192 mm  19.2 mm Number of barrels2 Inner barrel (6 ladders)r = 1.5 cm Outer barrel (18 ladders)r = 4.5 cm

6. 6 Selected Detector Parameters and Specifications Frame read time4 ms Pixel read rate, after zero suppression63 MHz Ladder % X 0 0.26% CoolingRoom temperature air, 1 m/s Power100 mW/cm 2

7. 7 Conceptual mechanical design

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13. 13  With the standard CMOS pixel array off chip CDS is required to remove fixed pattern noise and KTC reset noise  In the standard CMOS pixel array the signal is spread over multiple diodes uPenalty in signal to noise  Potential advantages of photo-gate uUse like CCD – read voltage, transfer charge – read voltage again and take difference. Gives on chip CDS uIncrease signal by reducing signal spreading to adjacent pixels. The photo gate permits large geometry without adding capacitance to the sense node. Photo gate purpose – to address standard pixel limitations P- P P+ Standard diode geometry

14. 14 photo gate source follower gate reset gate transfer gate row select gate sense node drain  Large photo-gate to collect large fraction of the charge on a single pixel, directly on the p- epi layer  Small transfer gate also directly on p- epi layer  Small drain (minimum capacitance) connected to source follower gate (sense node) Photo-gate geometry 20  m x -2  m- 1  m 5 nm 8  m 0.1  m 0.4  m P epi 1.4x10 15 1/cm 3 N+ 1x10 20 1/cm 3 photo gate transfer gate drain x = 0.4 and 0.8  m (simulation quantities) Chip designed and built by Stuart Kleinfelder and Yandong Chen UC Irvine

15. 15 Drain current after light injection  Nano amp drain current  Rapid electron transfer - complete in 60 ns photo gate transfer gate drain Light injection 60 ns Simulation using SILVACO ATLAS running on laptop. Service through eecad, only a few 10s of dollars to run. About to change to per day cost of ~$170 Relied on Zhang Li and Wei Chen to get started

16. 16 First silicon tests Photo-gate directly to sense node drain DC bias: V photo-gate 0.6 V V drain 2.4 V Accumulated histogram of output signal for Fe55 X-ray test after CDS correction  Signal spreading  Reduced gain Issues:

17. 17 Photo-gate LED test  Used a single pixel in sector 5 (simple structure with photo- gate and small drain on the edge) uPhoto-gate voltage 1 volt uDrain voltage set by full reset voltage  Test sequence uReset all pixels uClock row and column shift registers to select a single pixel uInject 2 red LED pulses uObserve output voltage with oscilloscope throughout sequence  Also did same test with sector 1 ( the standard diode) for comparison Sector 5 Photo-gate drain

18. 18 Measured output voltage Pulse 1 Pulse 2  Features to note uBoth sectors exposed to same LED pulses, but light attenuated for sector 1 uSector 5 response to 1 st LED pulse much smaller than to 2 nd uSector 5 leakage current ramp increases after 1 st LED pulse uResponse difference for the two pulses in sector 5 is directly related to gate, since sector 1 shows that readout structures are not affected differently by the two pulses uReducing the pulse separation did not change effect Standard pixel diode Photo-gate 200  s

19. 19 Photo-gate time response to two pulses the same, only amplitude difference Pulse 1 Pulse 2 Adjust amplitude and overlay Signal fits: + plus leakage slope   204  s

20. 20 Photo-gate  Test chip uMeasured charge transfer (200  s)  Can surface states explain the delay, calculate expectations uThe transfer process uRate of direct transfer, diffusion from gate to drain uRate of surface state population  Determine density of electrons at SiO 2 – Si surface uTime for surface state decay back to conduction band  Can this account for delay

21. 21 First step of electron collection Diffusing electrons caught in the vertical space charge field under the gate Gate Drain Electrons distribute along the surface

22. 22 Next step – getting to the drain Gate Drain The number of electrons under the gate I direct Direct drain current I trapped Trapping current I delayed Detrapping drain current Don’t need to solve equation to check for delay Determine if I direct <<I trapped and I delayed is small then signal collection is slow, more electrons spend time bound in surface states Surface states

23. 23 Simple diffusion transfer of electrons from gate to drain Diffusion equation in 1D Solve with COSMOS FEA (~3D) – thermal transient solution, analogous diffusion equation Result:  n = 120 ns Start with uniform temperature and a heat sink at the drain Convert to electron diffusion photo-gate drain total electrons under gate

24. 24 Silicon electric field under the gate Ey d Using Gaussian pill box = ~ 1.0 V since no inversion charge, ignoring work function differences p - epi p - epi with n type drain

25. 25 Density of electrons at the surface left by LED transient layer of 4000 electrons left by LED signal under 20  m  20  m gate d y LED Integrate over volume under gate to get n s 1/e distance = 12 nm

26. 26 Rate of capture into surface states Capture to surface states faster than direct diffusion to drain therefore surface states will affect transfer rate  st = 75 ns <  n = 120 ns capturedirect diffusion Measured by C vs freq, see Sze Use number of empty traps

27. 27 Energy window for contributing traps – how many traps Less than 100  s decay time Sze Traps already filled Decay time constant back to the conduction band, Zhang Li paper Number of contributing traps More than 15 ms decay time

28. 28 Number of empty traps is reasonable  10000 - The number of empty traps from the Sze plot which were empty and had a lifetime of more than 100  s uA plausible number for the trapping time ( 75 ns ) uA plausible number for saturation with the estimated 4000 photo generated electrons

29. 29 Leakage Current measured as a function of gate voltage The Read Shockley Hall leakage current from surface states should be large when depleted and should diminish when space charge is neutralized. Expected region where no longer depleted, but still a puzzle As suggested by Pavel. A measure of leakage current as a function gate voltage down below depletion voltage Same as a gated diode expected measured

30. 30 Density of surface states from leakage current Measured leak 16% of the Sze value used for trap capture time not in thermal equilibrium

31. 31 Concluding remarks  Some questions remain, but surface traps could explain photo-gate behavior uThey provide delay on right order uThey seem to have right number to see saturation effects uThey are consistent with observed leakage current  Another significant problem is the large leakage current, 10 times larger than pixel diode  Note, both Turchetta and Janesick tell me they have tried and failed to make a working photo-gate in standard CMOS. Janesick saw the same type of delayed signal  Janesick has made photo-gates work using a special process from Jazz Semiconductor with buried channel -- big bucks  Will there eventually be a photo process that available to us with buried channel?

32. 32 Evidence for saturated traps using 2 equal LED pulses? reset closed then open Vout two equal LED pulses reset

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34. 34 Recombination rate at surface = 0 if in thermal equilibrium Totally depleted even with LED pulse Large leakage current no recombination