1. M U N - February 15, 2005 - Phil Bording1 Computer Engineering of Wave Machines for Seismic Modeling and Seismic Migration R. Phillip Bording February 15, 2004 0 Max Address Husky Energy Chair in Oil and Gas Research Memorial University of Newfoundland

2. Session 1 History of Design Tyco Brahe Napier Charles Babbage – mechanical design John Atanasoff – Storage – spinning capacitor - Konrad Zuse - Floating Point Mauchley and Ekert von-Neumann Harvard memory – code memory - data Princeton memory code and data

3. Session 2 Current Design Issues Scaling laws Moore’s Law Transistors – VLSI Memory – Technology Division of Design The memory Challenge The processor Challenge The ILLIAC – PEPE IBM 7094 IBM 360/44 IBM 360/95 Array Processors the software of array processor calls

4. M U N - February 15, 2005 - Phil Bording4 Application Specific Machines

5. M U N - February 15, 2005 - Phil Bording5

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10. 10 Computing and Calculating Engines

11. M U N - February 15, 2005 - Phil Bording11 Session 1 History Vector memory Pipeline Arithmetic – Array Processing Vector memory Benchmark Driven Dollars Fairhair Syndrome

12. M U N - February 15, 2005 - Phil Bording12 Processors Data Memory Alu Hardwired instructions Processor Bottleneck Memory Bottleneck Vacuum tubes Core Plated Wire Transistors LSI – 6 T Static VLSI - 2 T Dynamic

13. M U N - February 15, 2005 - Phil Bording13 Linear Address Space Address Pointer 0 Max Address Latency is the time to access the first word Bandwidth is the rate of accessing successive words

14. M U N - February 15, 2005 - Phil Bording14 von Neumann Architecture Princeton Address Pointer Arithmetic Logic Unit (ALU) Memory Program Counter Pc = Pc + 1 Data/Instructions Featuring Deterministic Execution

15. M U N - February 15, 2005 - Phil Bording15 After Gustfason 2004 Bednar, 2004

16. M U N - February 15, 2005 - Phil Bording16 Bank memory design Duplicate memory system One design for subsystem Use a binary tree design to spread out addresses and data Fetch/Store many words at once Assume a sequential addressing pattern

17. M U N - February 15, 2005 - Phil Bording17 Bank memory design The wires created a big switch between modules The slower memory access time was better matched to the faster processor times Costly to build – significant effort in engineering

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21. M U N - February 15, 2005 - Phil Bording21 Array memory design N columns N rows NxN bits M bits on Bus

22. M U N - February 15, 2005 - Phil Bording22 Array memory design Streaming data flow, nibbles, bytes, and words Sequential Access First word access time = add+latency+data Successive words = data Random Access Indirect Addressing Non-uniform Strides

23. M U N - February 15, 2005 - Phil Bording23 Benchmark Scalar operations Array operations Do loop domination of codes Vendors look seriously at instruction stream Then comes Linpack. LU decomposition If it does matrix multiply fast nothing else matters or does it???

24. M U N - February 15, 2005 - Phil Bording24 Fairhair Syndrome New world class machine is designed at MIT, Stanford, or Caltech Venture Capital flows in Federal Government buys 10 new machines Company goes public Vulture capitalists sell out Federal Government buys new machines from someboldy else -- the next fairhair Company has stock scandal – goes bankrupt

25. Session 2 Current Design Issues Scaling laws Moore’s Law Transistors – VLSI Memory – Technology Division of Design The memory Challenge The processor Challenge The ILLIAC – PEPE IBM 7094 IBM 360/44 IBM 360/95 Array Processors the software of array processor calls