1. Microprocessor & Assembly Language Arithmetic and logical Instructions

2. The Addition Instructions The addition instructions take the forms: ADD destination, source ; destination = destination + source –add reg, reg ; reg 8, reg 16 or reg 32, Both source and destination operands must be the same size. –add reg, mem –add mem, reg –add reg, immediate data –add mem, immediate data –adc ( add with carry) forms are identical to ADD. –inc reg –inc mem –inc reg16 –xadd mem, reg –xadd reg, reg

3. ADD and ADC The addition instructions take the forms: –ADD destination, source ; destination = destination + source –ADC destination, source ; destination = destination + source+C –where C represents the value in the carry flag Both instructions affect the flags identically. They set the flags as follows: –The overflow flag denotes a signed arithmetic overflow. –The carry flag denotes an unsigned arithmetic overflow. –The sign flag denotes a negative result (i.e., the MSB bit of the result is one). –The zero flag is set if the result of the addition is zero. –The auxiliary carry flag contains one if a BCD overflow out of the L.O. nibble occurs. –The parity flag is set or cleared depending on the parity of the L.O. eight bits of the result. If there are an even number of one bits in the result, the ADD instructions will set the parity flag to one (to denote even parity). If there are an odd number of one bits in the result, the ADD instructions clear the parity flag (to denote odd parity).

4. ADD Examples J = K + J mov ax, K ; This works because addition is add J, ax ; commutative! J := J + 2 add J, 2 J = K + M + N + P mov ax, K add ax, M add ax, N add ax, P mov J, ax ADD BYTE PTR [DI],3 ;A 3 adds to the byte contents of the data segment memory location addressed by DI with the sum stored in the same location AL = Array [3] +Array [5] +Array [7] MOV AL,0 ;clear sum MOV SI,3 ;address element 3 ADD AL,ARRAY[SI] ;add element 3 ADD AL,ARRAY[SI+2] ;add element 5 ADD AL,ARRAY[SI+4] ;add element 7

5. ADC Examples ADC instruction mainly appears in software that adds numbers that are wider than 16 bits in the 8086–80286 or wider than 32 bits in the 80386– Core2 Examples:

6. The INC Instruction The inc (increment) instruction adds one to its operand. Except for the carry flag, inc sets the flags the same way as add operand, 1 The inc instruction is more compact and often faster than the comparable add reg, 1 or add mem, 1 instruction. Inc instruction does not affect the carry flag Examples: E.g.

7. The XADD Instructions Xadd (Exchange and Add) ( 80486 and later) instruction The following algorithm describes the operation of XADD instruction: xadd dest, source temp = dest dest = dest + source source = temp The xadd sets the flags just as the add instruction would The xadd instruction allows eight, sixteen, and thirty-two bit operands. Both source and destination operands must be the same size For example, if BL= 12H and Dl=02H after executing XADD BL,DL –BL = 14H, DL = 12H

8. The Subtraction Instructions The sub (subtract), sbb (subtract with borrow), dec (decrement) Their syntax is very similar to that of the add instructions: sub reg, reg sub reg, mem sub mem, reg sub reg, immediate data sub mem, immediate data sbb forms are identical to sub dec reg dec mem SUB destination, source ; destination=destination – source SBB destination, source ; destination=destination – source-C DEC destination ; destination=destination – 1

9. Subtraction Examples

10. Subtraction and flag register The sub, sbb, and dec instructions affect the flags as follows: –They set the zero flag if the result is zero. This occurs only if the operands are equal for sub and sbb. The dec instruction sets the zero flag only when it decrements the value one. –These instructions set the sign flag if the result is negative. –These instructions set the overflow flag if signed overflow/underflow occurs. –They set the auxiliary carry flag as necessary –They set the parity flag according to the number of one bits appearing in the result value. –The sub and sbb instructions set the carry flag if an unsigned overflow occurs, the dec instruction does not affect the carry flag

11. The CMP Instruction The comparison instruction (CMP) is a subtraction that changes only the flag bits; the destination operand never changes A comparison is useful for checking the entire contents of a register or a memory location against another value A CMP is normally followed by a conditional jump instruction, which tests the condition of the flag bits The cmp instruction is very similar to sub, the generic form is –cmp dest, src

12. CMP Example The cmp instruction updates the flags according to the result of the operation of subtraction if the instruction is cmp ax, bx: meaningFlag bit Z=1 if ax= bxZero flag(Z) S=1 if the result is negativeSign flag(S) O=1 if the result produced an overflow or underflow. Overflow flag(O) C=1 when ax is less than bx where ax and bx are both unsigned values. Carry flag(C) The cmp instruction also affects the parity and auxiliary carry flags,

13. Multiplication and Division Earlier 8-bit microprocessors could not multiply or divide without the use of a program that multiplied or divided by using a series of shifts and additions or subtractions Pentium–Core2 contains special circuitry to do multiplication in as little as one clocking period – it took over 40 clocking periods to perform the same multiplication in earlier Intel microprocessors.

14. Multiplication Multiplication is performed on bytes, words, or doublewords Multiplication can be signed integer (IMUL) or unsigned integer (MUL) The product after a multiplication is always a double- width product –If two 8-bit numbers are multiplied, they generate a 16-bit product – if two 16-bit numbers are multiplied, they generate a 32- bit product –if two 32-bit numbers are multiplied, a 64-bit product is generated

15. Multiplication Some flag bits (overflow and carry) change when the multiply instruction executes and produce predictable outcomes The other flags also change, but their results are unpredictable and therefore are unused Affected flags are C, and O. –Set: if higher byte of result not zero –Reset: the result fit exactly the lower half

16. Multiplication Instructions There are two forms of the multiply instruction: an unsigned multiplication (mul) and a signed multiplication (imul) The forms of multiply instructions –Unsigned Multiplication: mul reg mul mem –Signed (Integer) Multiplication: imul reg imul mem imul reg, reg, immediate imul reg, mem, immediate imul reg, immediate imul reg, reg imul reg, mem

17. 8-Bit Multiplication With 8-bit multiplication, the multiplicand is always in the AL register, signed or unsigned –multiplier can be any 8-bit register or memory location –mul operand8 ; ax = al * operand8 –imul operand8 ; ax = al * operand8 –Examples:

18. 16-Bit Multiplication Word multiplication is very similar to byte multiplication. AX contains the multiplicand instead of AL –32-bit product appears in DX–AX instead of AX –The DX register always contains the most significant 16 bits of the product; AX contains the least significant 16 bits dx:ax = ax * operand 16 Example:

19. 32-Bit Multiplication Contents of EAX are multiplied by the operand specified with the instruction The 64 bit product is found in EDX–EAX, where EAX contains the least significant 32 bits of the product –edx:eax = eax * operand 32 Examples:

20. Division division occurs on 8- or 16-bit numbers in the 8086– 80286 microprocessors, and on 32-bit numbers in the 80386 and above microprocessor Signed (IDIV) or unsigned (DIV) integers –div reg For unsigned division –div mem –idiv reg For signed division –idiv mem The dividend is always a double-width dividend that is divided by the operand None of the flag bits change predictably for a division

21. Division A division can result in two types of errors: – attempt to divide by zero – divide overflow  When the quotient too large to fit into the eax, ax, or al register.  Ex: AX=1300 / 2 the result 1500 in AL cause and overflow. In either case, the microprocessor generates an interrupt if a divide error occurs. In most systems, a divide error interrupt displays an error message on the video screen. Divide by an immediate value not allowed –You must load the immediate value into a register or a memory location and do the division through that register or memory location.

22. 8-Bit Division Uses AX to store the dividend divided by the contents of any 8-bit register or memory location. –Quotient in AL –Remainder in AH – quotient is positive or negative – remainder always assumes sign of the dividend; always an integer Numbers usually 8 bits wide in 8-bit division –the dividend must be converted to a 16-bit wide number in AX ; accomplished differently for signed and unsigned numbers –For the unsigned number, the most significant 8 bits must be cleared to zero (zeroextended). The MOVZX instruction can be used to zero-extend a number in the 80386 through the Core2 processors –For singed numbers, the least significant 8 bits are sign-extended into the most 8 bits CBW MOVSX

23. 8-Bit Division Examples: MOV AL,NUMB ;get NUMB MOV AH,0 ;zero-extend DIV NUMB1 ;divide by NUMB1 MOV ANSQ,AL ;save quotient MOV ANSR,AH ;save remainder

24. 16-Bit Division 16-bit division is similar to 8-bit division, except that instead of dividing into AX, the 16-bit number is divided into DX– AX, a 32-bit dividend – The quotient in AX and the remainder in DX If a 16-bit unsigned number is placed in AX, DX must be cleared to zero –the number is zero-extended by using the MOVZX instruction. If AX is a 16-bit signed number – the CWD and MOVSX can be used to sign-extend a number. –Example J := K / M (unsigned) mov ax, K ;Get dividend mov dx, 0 ;Zero extend unsigned value in AX to DX. div M mov J, ax

25. 32-Bit Division The 64-bit contents of EDX–EAX are divided by the operand specified by the instruction – 32-bit quotient in EAX and a 32-bit remainder in EDX The CDQ instruction is used before a signed division to convert the 32-bit contents of EAX into a 64-bit signed number in EDX–EAX –Example MOV EAX,–100 ;load a –100 MOV ECX,9 ;load +9 CDQ ;sign-extend IDIV ECX