1. Recall Lecture 17 MOSFET DC Analysis 1.Using GS (SG) Loop to calculate V GS Remember that there is NO gate current! 2.Assume in saturation Calculate I D using saturation equation 3.Find V DS (for NMOS) or V SD (for PMOS) Using DS (SD) loop 4.Calculate V DS sat or V SD sat 5.Confirm that V DS > V DS sat or V SD > V SD sat Confirm your assumption!

2. APPLICATION OF MOSFETS

3. Digital Logic Gates NOR gateNAND gate NOR gate response The NAND gate response 00High 00 50Low 50High 05Low 05High 55Low 55

4. CHAPTER 7 Basic FET Amplifiers

5. For linear amplifier function, FET is normally biased in the saturation region.

6. AC PARAMETERS where

7. The MOSFET Amplifier - COMMON SOURCE The output is measured at the drain terminal The gain is negative value Three types of common source – source grounded – with source resistor, R S – with bypass capacitor, C S

8. Common Source - Source Grounded ●A Basic Common-Source Configuration: Assume that the transistor is biased in the saturation region by resistors R 1 and R 2, and the signal frequency is sufficiently large for the coupling capacitor to act essentially as a short circuit.

9. EXAMPLE V DD = 5V R si R D = 10 k  0.5 k  520 k  320 k  The transistor parameters are: V TN = 0.8V, K n = 0.2mA/V 2 and = 0. I D = 0.2441 mA g m = 0.442 mA/V

10. Steps 1.Calculate R out 2.Calculate v o ________________________________________________________ 3.Find v gs in terms of v i 4.Calculate the voltage gain, Av

11. 1.The output resistance, R out = R D 2.The output voltage: v o = - g m v gs (R out ) = - g m v gs (10) = -4.42 v gs 3.The gate-to-source voltage:, R i = R TH v gs = [198.1 / (198.1 + 0.5 )] = 0.9975 v i  v i = 1.0025 v gs 4.So the small-signal voltage gain: A v = v o / v i = - 4.42 v gs / 1.0025 v gs  - 4.41 R TH 198.1 k  0.5 k  R D = 10 k  0.442 v gs

12. Type 2: With Source Resistor, R S V TN = 1V, K n = 1.0mA / V

13. V G = ( 200 / 300 ) x 3 = 2 V Hence, KVL at GS Loop: V GS + I D R S – V TH = 0 V GS = 2 – 3I D KVL at DS loop V DS + 10 I D + 3I D – 3 = 0 V DS = 3 -13 I D Assume biased in saturation mode: Hence, I D = 1.0 (2 – 3I D - 1 ) 2 = 1.0 (1 – 3I D ) 2  9 I D 2 – 7 I D + 1 = 0 Perform DC analysis Assume transistor in saturation V TN = 1V, K n = 1.0 mA / V

14. I D = 0.589 mAI D = 0.19 mA V DS sat = V GS - V TN = 1.43 – 1.0 = 0.43 V 0.53 V > 0.43 V Transistor in saturation Assumption is correct! V GS = 2 – 3I D = 0.233 < V TN V GS = 2 – 3I D = 1.43 V > V TN MOSFET is OFF OK V DS = 3 -13 I D = 0.53 V Not OK

15. Steps 1.Calculate R out 2.Calculate v o ________________________________________________________ 3.Find v ’ in terms of v gs 4.Find v’ in terms of v i 5.Calculate the voltage gain, Av

16. 1.The output resistance, R o = R D 2.The output voltage: 3.Find v’ v ’ = v gs + g m v gs R S  v’ = v gs (1 + 2.616) = 3.616 v gs v o = - g m v gs R D = - 0.872 ( v gs ) (10) = - 8.72 v gs R TH 66.67 k  R D = 10 k  R S = 3 k  g m = 0.872 mA/V + V’ -

17. 5. Calculate the voltage gain A V = v o / v i = - 8.72 v gs / 3.616 v gs = - 2.41 4. Find v’ in terms of v i : using voltage divider R TH 66.67 k  R D = 10 k  R S = 3 k  + V’ - v’ = [R TH / (R si + R TH )] v i But in this circuit, R si = 0 so, v’ = v i = 3.616 v gs

18.  Circuit with Source Bypass Capacitor ●An source bypass capacitor can be used to effectively create a short circuit path during ac analysis hence avoiding the effect R S ●C S becomes a short circuit path – bypass R S ; hence similar to Type 1 Type 3: With Source Bypass Capacitor, C S

19. Steps 1.Calculate R out 2.Calculate v o ________________________________________________________ 3.Find v gs in terms of v i 4.Calculate the voltage gain, Av

20. I Q = 0.5 mA hence, I D = 0.5 mA g m = 2  K n I D = 1.414 mA/V r o =  R G 200 k  R D = 7 k  1.414 v gs

21. 1.The output resistance, R out = R D 2.The output voltage: v o = - g m v gs (R D ) = -1.414 (7) v gs = - 9.898 v gs 3. The gate-to-source voltage: v gs = v i  in parallel ( no need voltage divider) 4. So the small-signal voltage gain: A v = -9.898 v gs / v gs = - 9.898

22. The MOSFET Amplifier - COMMON DRAIN The output is measured at the source terminal The gain is positive value

23. R TH 150 k  470 k  0.75 k  113.71 k  0.5 k  I D = 8 mA, K n = 4 mA /V 2 g m = 2  K n I D = 11.3 mA/V

24. Steps 1.Calculate R out 2.Calculate v o ________________________________________________________ 3.Find v ’ in terms of v gs 4.Find v’ in terms of v i 5.Calculate the voltage gain, Av

25. 1.The output resistance: 2.The output voltage 3.v’ in terms of v gs using supermesh: 4.v’ in terms of v i : 5.The voltage gain v gs + g m v gs (r o  R S ) – v’ = 0 v’ = v gs + 8 v gs = 9 v gs v o = g m v gs (r o  R S ) = 11.3 v gs (0.70755) = 8 v gs v’ = (R TH / R TH + R Si ) v i = 0.9956 v i 9v gs = 0.9956 v i  v i = 9.040 v gs + v’ - g m = 2  K n I D = 11.3 mA/V A v = v o / v i = 8 v gs / 9.040 v gs = 0.885 R o = ro || R s

26. +-+- Vx Ix r o || R s = 0.708 k  v gs in terms of V x where v gs = -V x - V x + g m v gs + I x = 0 0.708 - V x - g m V x + I x = 0 0.708 - 1.412 V x – 11.3 V x + I x = 0 I x = 12.712 V x 0.079 k  Output Resistance for Common Drain