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-1- UC San Diego / VLSI CAD Laboratory Optimization of Overdrive Signoff Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li and Siddhartha Nath Tuck-Boon Chan,

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Presentation on theme: "-1- UC San Diego / VLSI CAD Laboratory Optimization of Overdrive Signoff Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li and Siddhartha Nath Tuck-Boon Chan,"— Presentation transcript:

1 -1- UC San Diego / VLSI CAD Laboratory Optimization of Overdrive Signoff Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li and Siddhartha Nath Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li and Siddhartha Nath VLSI CAD LABORATORY, UC San Diego

2 -2- Outline Motivation Motivation Design Cone Design Cone Dominance of Modes Dominance of Modes Problems and Methodologies Problems and Methodologies Experimental Setup and Results Experimental Setup and Results Conclusions and Ongoing Works Conclusions and Ongoing Works

3 -3- Outline Motivation Motivation Design Cone Design Cone Dominance of Modes Dominance of Modes Problems and Methodologies Problems and Methodologies Experimental Setup and Results Experimental Setup and Results Conclusions and Ongoing Works Conclusions and Ongoing Works

4 -4- Motivation Mode = (voltage, frequency) pair requires Multi-mode operation requires multi-mode signoff – –Example: nominal mode and overdrive mode Selection of signoff modes affects area, power Our Goal: Optimally select signoff modes  Improve performance, power, or area   Reduce overdesign NOM OD NOM OD time V dd t nom t OD t nom t OD

5 -5- Fix Nominal Mode f nom = 500MHz V nom = 0.9V < 87 mW 87 - 89 mW 90 - 92 mW 93 - 95 mW > 95 mW 1.051.071.091.111.131.151.171.03 1000 950 900 850 800 Overdrive Voltages (V) Overdrive Frequencies (MHz) 93 - 95 mW Different overdrive modes  20% power range The average power of circuits signed off with different overdrive modes Average power = r x P OD + (1-r) x P nom – –r is the duty cycle of overdrive mode

6 -6- Power of circuits signed off with different overdrive voltages Power of circuits signed off with different overdrive voltages  large # of buffers Low signoff voltage  large # of buffers  high dynamic power High signoff voltage  high dynamic power 14% f nom = 500MHz V nom = 0.9V f OD = 950MHz Fix Nominal Mode + OD Frequency

7 -7- Outline Motivation Motivation Design Cone Design Cone Dominance of Modes Dominance of Modes Problems and Methodologies Problems and Methodologies Experimental Setup and Results Experimental Setup and Results Conclusions and Ongoing Works Conclusions and Ongoing Works

8 -8- Tradeoff between Frequency & Voltage  frequency vs. voltage tradeoff curves Voltage scaling  frequency vs. voltage tradeoff curves Maximum frequency increases essentially linearly with supply voltage We approximate such curves as straight lines We approximate such curves as straight lines

9 -9- Design Space for Signoff Design space for signoff is Design space for signoff is the set of all possible combinations of signoff modes Example: design space for two-mode signoff is all combinations of two points in the plane Voltage Frequency Mode  (voltage, frequency) Circuit  (frequency vs. voltage tradeoff) curve

10 -10- Design Cone Design cone is the Design cone is the union of all the feasible operating modes (frequency, voltage pairs) for circuits signed off at one mode Determined by tradeoff between frequency and voltage (slopes of frequency vs. voltage tradeoffs) Indicates the solution space for signoff mode selection Voltage Frequency A The design cone of mode A

11 -11- Estimation of Design Cone Slope of frequency vs. voltage tradeoff (MHz/V) mainly determined by threshold voltages Gate type, fanout have little influence Wire resistance also has little influence –  <2% change in slopes –10,000X change in resistance  <2% change in slopes VTVT Fanout Gate Types INVNANDNOR LVT4887800936 LVT16776787877 HVT4116711761260 HVT16112612171246

12 -12- Estimation of Design Cone Slope of frequency vs. voltage tradeoff (MHz/V) mainly determined by threshold voltages Gate type, fanout have little influence Wire resistance also has little influence –  <2% change in slopes –10,000X change in resistance  <2% change in slopes VTVT Fanout Gate Types INVNANDNOR LVT4887800936 LVT16776787877 HVT4116711761260 HVT16112612171246

13 -13- Estimation of Design Cone Slope of frequency vs. voltage tradeoff (MHz/V) mainly determined by threshold voltages Gate type, fanout have little influence Wire resistance also has little influence –  <2% change in slopes –10,000X change in resistance  <2% change in slopes VTVT Fanout Gate Types INVNANDNOR LVT4887800936 LVT16776787877 HVT4116711761260 HVT16112612171246

14 -14- Estimation of Design Cone Slope of frequency vs. voltage tradeoff (MHz/V) mainly determined by threshold voltages Gate type, fanout have little influence Wire resistance also has little influence –  <2% change in slopes –10,000X change in resistance  <2% change in slopes VTVT Fanout Gate Types INVNANDNOR LVT4887800936 LVT16776787877 HVT4116711761260 HVT16112612171246

15 -15- Estimation of Design Cone Slope of frequency vs. voltage tradeoff (MHz/V) mainly determined by threshold voltages Gate type, fanout have little influence Wire resistance also has little influence –  <2% change in slopes –10,000X change in resistance  <2% change in slopes VTVT Fanout Gate Types INVNANDNOR LVT4887800936 LVT16776787877 HVT4116711761260 HVT16112612171246

16 -16- Estimation of Design Cone Slope of frequency vs. voltage tradeoff (MHz/V) mainly determined by threshold voltages We use inverter chains with LVT- and HVT-only cells to estimate the boundary of design cone

17 -17- Outline Motivation Motivation Design Cone Design Cone Dominance of Modes Dominance of Modes Problems and Methodologies Problems and Methodologies Experimental Setup and Results Experimental Setup and Results Conclusions and Ongoing Works Conclusions and Ongoing Works

18 -18- Dominance One mode is outside of the design cone of the other  positive / negative timing slacks One mode is outside of the design cone of the other  positive / negative timing slacks LVT HVT Voltage Frequency A Design Cone of mode A C Negative Slack Positive Slack B  Above the design cone  Negative timing slacks  Below the design cone  Positive timing slacks

19 -19- Dominance LVT HVT B Voltage Frequency A  Mode A is the dominant mode Design Cone of mode A One mode is outside of the design cone of the other  positive / negative timing slacks One mode is outside of the design cone of the other  positive / negative timing slacks M 2 shows positive timing slacks w.r.t. M 1  M 1 is the dominant mode M 2 shows positive timing slacks w.r.t. M 1  M 1 is the dominant mode

20 -20- Dominance One mode is outside of the design cone of the other  positive / negative timing slacks One mode is outside of the design cone of the other  positive / negative timing slacks M 2 shows positive timing slacks w.r.t. M 1  M 1 is the dominant mode M 2 shows positive timing slacks w.r.t. M 1  M 1 is the dominant mode LVT HVT B Voltage Frequency A B’  Mode A is the dominant mode  Shift mode B to B’  reduce voltage and power  retain same performance Design Cone of mode A Positive timing slacks indicate overdesign Positive timing slacks indicate overdesign Positive Slack

21 -21- Equivalent Dominance When two modes exhibit equivalent dominance – –No one is dominated by the other – –They are in each other’s design cone Mode A and B exhibit equivalent dominance Voltage Frequency A B Multi-mode signoff at modes which do not exhibit equivalent dominance leads to overdesign

22 -22- Outline Motivation Motivation Design Cone Design Cone Dominance of Modes Dominance of Modes Problems and Methodologies Problems and Methodologies Experimental Setup and Results Experimental Setup and Results Conclusions and Ongoing Works Conclusions and Ongoing Works

23 -23- Overdrive signoff has four parameters – –Nominal mode:, – –Overdrive mode:, The 3+1 Problems Given f nom, f OD and V nom, search for V OD Given f nom, f OD and V OD, search for V nom  Minimize power Given V nom, V OD and f nom, search for f OD Given V nom, V OD and f OD, search for f nom  Maximize performance under power constraints  Maximize performance under power constraints f nom V nom f OD V OD

24 -24- The 2+2 Problems Overdrive signoff needs four parameters – –Nominal mode: f nom, V nom – –Overdrive mode: f OD, V OD FIND_OD: given (f nom, V nom ), search for (f OD, V OD )  maximize f OD s.t. average and peak power satisfy constraints FIND_VOLT: given f nom and f OD, search for V nom and V OD  minimize average power

25 -25- Reduction from 2+2 to 3+1 2+2 problems can reduce to 3+1 problems by sweeping one unknown parameter f nom f OD f nom f OD Sweep V nom V nom_{1, 2,...} 3+1 Problem Solver V OD_1, V OD_2,... Miminum P avg Corresponding V nom V nom V OD f nom V nom f nom V nom Sweep V OD V OD_{1, 2,...} 3+1 Problem Solver f OD_1, f OD_2,... Maximum f OD Corresponding V OD f OD V OD Reduction of FIND_OD problem Reduction of FIND_VOLT problem

26 -26- Methodologies for 3+1 Problems Given f nom, f OD and V nom, search for V OD Given f nom, f OD and V OD, search for V nom  Minimize power Voltage Frequency Nominal Mode V nom f nom f OD Voltage Frequency Overdrive Mode V OD f nom f OD Solution space Exhaustive search on the solution space defined by given parameters and design cone

27 -27- Methodologies for 3+1 Problems Voltage Frequency Nominal Mode V nom f nom V OD Voltage Frequency Overdrive Mode V OD V nom f OD Solution space Scale frequency along the solution space until the power constraint is hit Given V nom, V OD and f nom, search for f OD Given V nom, V OD and f OD, search for f nom  Maximize performance under power constraints  Maximize performance under power constraints

28 -28- Common Design Practice Today: Signoff & Scale (FIND_OD) Sign off circuit at nominal mode Sign off circuit at nominal mode Frequency Voltage Nominal Mode V nom f nom V OD Overdrive Mode f OD Scale the voltage to increase frequency until the power constraint is hit Scale the voltage to increase frequency until the power constraint is hit Simplifies the design process, but ignores second (OD) mode in the signoff Simplifies the design process, but ignores second (OD) mode in the signoff

29 -29- Proposed Flow (FIND_OD) Signoff & scale at nominal mode to estimate the maximum overdrive frequency (f est ) Voltage Frequency Nominal Mode V nom f nom f est

30 -30- Proposed Flow (FIND_OD) Signoff & scale at nominal mode to estimate the maximum overdrive frequency (f est ) Determine several approximate overdrive modes based on f est and the design cone Voltage Frequency Nominal Mode V nom f nom f est Approximate overdrive modes

31 -31- Proposed Flow (FIND_OD) Signoff & scale at nominal mode to estimate the maximum overdrive frequency (f est ) Determine several approximate overdrive modes based on f est and the design cone Implement voltage scaling on each approximate overdrive mode until hit the power constraint Overdrive Mode (highest f OD ) Voltage Frequency Nominal Mode V nom f nom f est

32 -32- Proposed Flow (FIND_VOLT) Exhaustive search for V nom  minimum power at nominal mode Voltage Frequency f nom f OD Voltage Nominal power V nom

33 -33- Proposed Flow (FIND_VOLT) Exhaustive search for V nom  minimum power at nominal mode Estimate the design cone of selected mode Voltage Frequency f nom f OD Voltage V nom

34 -34- Proposed Flow (FIND_VOLT) Exhaustive search for V nom  minimum power at nominal mode Estimate the design cone of selected mode Exhaustive search for V OD within the design cone  minimum average power Voltage Frequency f nom f OD Voltage V nom V OD

35 -35- Outline Motivation Motivation Design Cone Design Cone Dominance of Modes Dominance of Modes Problems and Methodologies Problems and Methodologies Experimental Setup and Results Experimental Setup and Results Conclusions and Ongoing Works Conclusions and Ongoing Works

36 -36- Experimental Setup Design: AES (~15K instances) from OpenCores Technology: TSMC 65nm Comparison – –Signoff&Scale applies traditional signoff and scale methodology – –Proposed implements our proposed flow – –Exhaustive Search uses exhaustive search

37 -37- Experimental Results (FIND_OD) Proposed flow improves performance by 7% Signoff & ScaleProposed FlowExhaustive Search f OD (MHz)711764768 V OD (V)1.14 1.15 Area (µm 2 )310293201632020 P OD (mW)49.1349.1449.76 P avg (mW)21.7320.9020.24 # P&R runs17 32 Nominal mode: f nom = 500MHz V nom = 0.9V Flow requires about 22% runtime compared to exhaustive search with similar area (-0.01%), power (+3%) and performance (-0.5%)

38 -38- Experimental Results (FIND_VOLT) Flow requires about 27% runtime compared to exhaustive search with similar area (-0.01%), power (+8%) Proposed FlowExhaustive Search V nom (V)0.920.91 V OD (V)1.021.01 Area (µm 2 )3094830960 P OD (mW)41.08 30.38 P avg (mW)22.2820.61 # P&R runs9 33 f nom = 500MHz / f OD = 600MHz Signoff & Scale is not applicable to FIND_VOLT

39 -39- Recent Updates Problem: too many SP&R runs Approach: – –Use power models for global optimization – –Avoid implementing circuits at each mode Construct power model adaptively Small constant # runs is enough  scalable

40 -40- Global Optimization Flow Iteratively sample and refine the power models Sample (SP&R) Construct power models Estimate optimal signoff modes Estimate optimal signoff modes Sample (SP&R) Refine power models Circuit information Power models Estimated optimal mode Circuit information

41 -41- Example Performance of the proposed global optimization Frequency = 800MHz, Voltage = ? 0.90V 1.20V 1.10V 1.08V 1.06V

42 -42- Outline Motivation Motivation Design Cone Design Cone Dominance of Modes Dominance of Modes Problems and Methodologies Problems and Methodologies Experimental Setup and Results Experimental Setup and Results Conclusions and Ongoing Works Conclusions and Ongoing Works

43 -43- Conclusions & Ongoing Works Conclusions – –Study the problem of signoff mode selection – –Propose the concept of design cone – –Show that mutual equivalent dominance is required for signoff mode selection to avoid overdesign – –Propose methodologies for signoff mode selection Ongoing Works – –More accurate estimation of design cone – –Consider additional tradeoffs of design metrics such as area, reliability

44 -44- Acknowledgments Work supported by IMPACT, SRC, NSF, Qualcomm and Samsung

45 -45- Thank You!

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