1. System IC Design Lab. Dongguk University 1 Chip design Chip design KIM,D.H., KWON,Y.,SONG,M.K. Department of Semiconductor Science, Dongguk Univ. for the ALICE collaboration. Department of Physics, Yonsei Univ. for the ALICE collaboration.

2. System IC Design Lab. Dongguk University 2 I.pALPIDEfs – work on DACs II.pALPIDEfs version 2 – work on I/O PAD III.Next plan

3. System IC Design Lab. Dongguk University 3 I. pALPIDEfs – work on DAC - Layout of pALPIDEfs Pixel Matrix: sensitive area Periphery circuit ( DACs, PADs, periphery readout logic, etc) Matrix DACs Periphery Logic I/O pads

4. System IC Design Lab. Dongguk University 4 I. pALPIDEfs – work on DAC DAC - List of Voltage and Current DACs Voltage DACCurrent DAC Resolution8bit TypeResistorpMOS Output/unitcolu mn 6EA 1) V CASP 2) V CASN 3) V RESET 4) V PULSE _ LOW 5) V PULSE _ HIGH 6) V AUX 5EA 1) I BIAS 2) I THR 3) I DB 4) I AUX 1 5) I AUX 2

5. System IC Design Lab. Dongguk University 5 I. pALPIDEfs – work on DAC DAC – Voltage DAC VCASPVCASNVRESET VPLSE_L OW VPLSE_HI GH VRESET 000368mV 2551.8V VREF AVSS Block diagram & Simulation result

6. System IC Design Lab. Dongguk University 6 I. pALPIDEfs – work on DAC DAC – Current DAC Block diagram & Simulation result Current DAC Current reductio n SLOW @ 1.62V, 60°C NOM @ 1.8V, 27°C FAST @ 1.98V, 0°C 02550 0 IBIAS 1 : 128 90pA15nA300pA80.4nA2nA500nA ITHR 1 : 4096 10pA0.65nA12pA2.56nA60pA15.5nA IDB 1 : 256 46pA10.6nA162pA41.7nA1nA259nA IRESET 1 : 256000 0.8pA2.56pA0.7pA26.2pA0.9pA192pA IAUX2 1:1 Not used

7. System IC Design Lab. Dongguk University 7 II. pALPIDEfs Version 2 – work on PAD - Specification of I/O PAD Property of Cable R=170mΩ/cm @ W= 100um C=1pF/cm @ W= 100um 100um 21cm R CABLE = 3.57 Ω C CABLE = 21pF 3.57 Ω 21pF 6pF 10 Ω 50 Ω Pull down or Pull up Total Load at the output driver R LOAD = 3.57Ω + 10 Ω ≈ 14Ω C LOAD = 6pF x 7 + 21pF ≈ 65pF 40 kΩ DVDD or DVSS 40 kΩ DVDD or DVSS Pull down or Pull up

8. System IC Design Lab. Dongguk University 8 II. pALPIDEfs Version 2 – work on PAD - design of I/O PAD 92um 90um CIN OEN D_OUT PAD DVSS DVDD AVSS AVDD SUB ESD diode Buffer & Resistor CIN OEN D_OUT PAD CIN DOUT

9. System IC Design Lab. Dongguk University 9 II. pALPIDEfs Version 2 – work on PAD - Simulation result of I/O PAD CIN OEN D_OUT PAD Type Structure Type Result Standard Core Input Transition = 0.5 ns Pad Load = 4Ω,65pF Slow (80°C)Normal (25°C)Fast (0°C) RisingFallingRisingFallingRisingFalling R1 = 10 Ω for pro tect buff er, 1x buffer Outpu t Driver (Core  PA D) Transi(ns) 4.965.434.11 3.293.61 tCMOS(ns) 3233.762.502.801.96232 tOE(ns) 6.306.204.604.663.814.06 Input Buffer (PAD  Cor e) Transi(ns) 0.580.260.440.180.340.15 tCD(ns) 0.560.440.410.340.310.28 Power DVDD(pJ) Tot.Int.Load.Tot.Int.Load.Tot.Int.Load. 174.64170.6215.95.3210.6261.97.1254.8 Dout Post simulation result of PAD_I/O (with parasitic parameter)  Output driver : Delay < 5ns @ Load : 4Ω, 65pF  Input buffer : Load : 0.5Ω, 160fF

10. System IC Design Lab. Dongguk University 10 III. Next plan - Study of discriminator CIN OEN D_OUT PAD Analysis of front-end and design new structure

11. System IC Design Lab. Dongguk University 11 Thank you