1. Embedded Systems Design with Qsys and Altera Monitor Program
Tutorial #2

2. Material for teaching embedded systems
Tutorials on Altera’s embedded processors
Nios II
ARM Cortex A9
Lab exercises that use these processors
Set context for talking about the ARM processor. Want to teach you how to use the DE1-SoC which has the ARM processor on it. This course we will focus on the ARM processor.

3. ARM Cortex A9 Processor + programmable FPGA
Cyclone V SoC
ARM Cortex A9 Processor + programmable FPGA
Cyclone V SoC
ARM Hard Processor System
FPGA

4. Altera HPS Block Diagram
ARM

5. Altera HPS Block Diagram
4 GB
HPS
ARM
3 GB
L2 Cache
2 GB
1 GB
0 GB

6. Altera HPS Block Diagram
4 GB
HPS
ARM
3 GB
L2 Cache
L3 Interconnect
2 GB
1 GB
0 GB

7. Altera HPS Block Diagram
4 GB
HPS
ARM
3 GB
Boot ROM
L2 Cache
2 GB
1 GB
Boot Region
0 GB

8. Altera HPS Block Diagram
4 GB
HPS
ARM
3 GB
SDRAM
Window
Boot ROM
L2 Cache
2 GB
SDRAM
Controller
1 GB
DDR3
Chips
Boot Region
0 GB

9. Altera HPS Block Diagram
4 GB
HPS
ARM
3 GB
SDRAM
Window
Boot ROM
L2 Cache
2 GB
SDRAM
Controller
Previously we ran starting at addr 0 that’s because AMP automatically extended the SDRAM window all the way down to 0
1 GB
DDR3
Chips
Boot Region
0 GB

10. Altera HPS Block Diagram
4 GB
HPS
ARM
3 GB
SDRAM
Window
On-Chip RAM
Boot ROM
L2 Cache
2 GB
SDRAM
Controller
Bunch of peripherals like onchip memory
1 GB
DDR3
Chips
Boot Region
0 GB

11. Altera HPS Block Diagram
4 GB
HPS
ARM
Timers
3 GB
SDRAM
Window
On-Chip RAM
Boot ROM
L2 Cache
2 GB
SDRAM
Controller
1 GB
DDR3
Chips
Boot Region
0 GB

12. Altera HPS Block Diagram
4 GB
HPS
ARM
Timers
3 GB
SDRAM
Window
On-Chip RAM
Boot ROM
L2 Cache
2 GB
GPIO
SDRAM
Controller
1 GB
LEDG
KEY
DDR3
Chips
Boot Region
0 GB

13. Altera HPS Block Diagram
4 GB
HPS
ARM
Timers
3 GB
SDRAM
Window
On-Chip RAM
Boot ROM
L2 Cache
2 GB
Ports
GPIO
SDRAM
Controller
1 GB
USB
Ethernet
LEDG
KEY
DDR3
Chips
Boot Region
0 GB

14. Altera HPS Block Diagram
4 GB
HPS
Peripherals
ARM
Timers
3 GB
SDRAM
Window
On-Chip RAM
Boot ROM
L2 Cache
2 GB
Ports
GPIO
SDRAM
Controller
1 GB
USB
Ethernet
LEDG
KEY
DDR3
Chips
Boot Region
0 GB

15. How About Communication with the FPGA?
4 GB
HPS
FPGA
Peripherals
ARM
Timers
3 GB
SDRAM
Window
On-Chip RAM
Boot ROM
L2 Cache
2 GB
Ports
GPIO
SDRAM
Controller
1 GB
USB
Ethernet
LEDG
KEY
DDR3
Chips
Boot Region
0 GB

16. There are Several Bridges Between the HPS and FPGA
4 GB
HPS
FPGA
Peripherals
ARM
Timers
3 GB
SDRAM
Window
On-Chip RAM
Boot ROM
L2 Cache
Bridges
2 GB
Ports
GPIO
SDRAM
Controller
1 GB
USB
Ethernet
LEDG
KEY
DDR3
Chips
Boot Region
0 GB

17. HPS-to-FPGA Bridge 4 GB HPS FPGA Peripherals ARM FPGA Slave Region
Timers
3 GB
SDRAM
Window
On-Chip RAM
Boot ROM
On-Chip
Cores
L2 Cache
H2F
2 GB
Ports
GPIO
SDRAM
Controller
Ports
This bridge will lalow you to connect any peripheral in FPGA to ARM processor. Addr range is shown in the light blue.
1 GB
USB
Ethernet
LEDG
KEY
DDR3
Chips
LEDR
Switches
Etc.
Boot Region
0 GB

18. Lightweight HPS-to-FPGA Bridge
4 GB
HPS
FPGA
Peripherals
ARM
FPGA
Slave
Region
Timers
3 GB
SDRAM
Window
On-Chip RAM
Boot ROM
On-Chip
Cores
L2 Cache
LW H2F
2 GB
Ports
GPIO
SDRAM
Controller
Ports
Much smaller addr range, within peripherals region. HPS bridge is large bridge with low latency for bulk transfers. LW bridge is usually used to communicate with control registers, and communication thru this bridge will not interrupt bulk transfers on the bigger HPS bridge.
1 GB
USB
Ethernet
LEDG
KEY
DDR3
Chips
LEDR
Switches
Etc.
Boot Region
0 GB

19. Use Qsys and Quartus to Create the FPGA Portion1
4 GB
HPS
FPGA
Peripherals
ARM
FPGA
Slave
Region
Timers
3 GB
SDRAM
Window
On-Chip RAM
Boot ROM
On-Chip
Cores
L2 Cache
LW H2F
2 GB
Ports
GPIO
SDRAM
Controller
Ports
Much smaller addr range, within peripherals region. HPS bridge is large bridge with low latency for bulk transfers. LW bridge is usually used to communicate with control registers, and communication thru this bridge will not interrupt bulk transfers on the bigger HPS bridge.
1 GB
USB
Ethernet
LEDG
KEY
DDR3
Chips
LEDR
Switches
Etc.
Boot Region
0 GB

20. Quartus System Integration Tool (Qsys)
Tool for connecting components to create a system. Use prebuilt componenets, but can create your own as well. Qsys will generate all of the interconnect fabric for you.

21. Qsys Windows Selected Components And connectivity Available Components
Available components listed in the library window. Your own components that you’ve added will be in list as well. Main system subwindow that shows selected components and their connectivity. Messages window to show info messages…
Available
Components
Messages

22. Select Components to add to the System

23. Configure the Components using their Wizards

24. HPS Component: Adding/Removing FPGA to SDRAM Bridges

25. HPS Component: Editing HPS Peripherals

26. HPS Component: Editing SDRAM Parameters

27. Component is now in the System

28. Creating a System in Qsys General Steps
Select a processor
Altera HPS or a Nios
Add off-the-shelf with standard interfaces (SPI, I2C, JTAG, etc.) to help solve the problem
Use existing drivers or write one yourself
Sometimes an existing driver needs to be augmented for a particular application
Add custom components when the needed ones are not available (or too expensive)
Add I/O as needed
Write code to run on the system
Usually a single program

29. How to put them together?
Qsys system integration tool
Add components
Generate the System HDL
Quartus II software
Synthesize HDL for the FPGA
Altera Monitor Program
Compile and debug software

30. Exercise 4: Making a Custom System
Use Qsys to make a system with:
Altera HPS component
PIO cores for:
Red LEDs
Seven Segments Displays
Slider switches
Compile the system using the Quartus II software

31. Step 1: Open the DE1_SoC Project in Quartus II

32. Step 2: Open the DE1_SoC Project in Quartus II

33. Step 3: Launch Qsys

34. Step 4: Select the Computer System

35. Step 5: The Pre-Started System

36. Step 6: Add PIO Component for the LEDRs

37. Step 7: Configure the PIO for the LEDRs

38. Step 8: Add and Configure a PIO for the 7-Segs

39. Step 9: Add and Configure a PIO for the Switches

40. Step 10: Current System

41. Step 11: Export PIOs’ External Connections
Connect the external ports by exporting the external_connection port of the components.

42. Step 12: Minimize the PIOs

43. Step 13: Make Connections

44. Step 14: Go to Address Map Tab
Have been mapped to the same address range within the lw bridge…

45. Step 15: Set the Slave Addresses
These are the OFFSETS into the lw bridge. These will result in these registers being placed at the same addresses as the previous example.

46. Step 16: Generate the System
Now we can see that the errors and warnings are gone. We can generate the system!

47. Step 17: Generate the System
Bunch of options.. we]’ll use the default settings.

48. Step 18: System Generation Finished

49. Step 18: Generated System
module Computer_System (
clk_clk,
reset_reset_n,
// LEDs
ledr_export,
// Seven Segs
hex3_hex0_export,
// Slider Switches
sw_export,
... );
FPGA
LEDs
HPS
7-Segs
Switches

50. Step 19: Create Top Level File for project
System must be instantiated in your design
Must connect system ports to the I/O ports
In this demo the top level file has been created for you
Compile your project.
Open the DE1_SoC.v to examine the system connectivity while Quartus II compiles the project.

51. Step 20: Compile the System in Quartus II

52. Step 21: Wait for Compilation to Finish

53. What Exactly Did We Just Build?
Two files:
.sopcinfo file (qsys)
.sof file (quartus)
HPS
FPGA
ARM … … …
pio_2 .
LW H2F … … …
pio_1
pio_0
Much smaller addr range, within peripherals region. HPS bridge is large bridge with low latency for bulk transfers. LW bridge is usually used to communicate with control registers, and communication thru this bridge will not interrupt bulk transfers on the bigger HPS bridge.

54. Please read the instructions at
Hands-On Session
Please read the instructions at
“/exercise4/instructions.pdf”
Use provided Quartus project “DE1_SoC.qpf”
Use pre-started Qsys system “”Computer_System.qsys”
We will be walking around to help with any issues

55. Exercise 5: Developing an Embedded Application
Write a software application to run on the system that we built in the previous exercise
Compile the code using Altera Monitor Program
Run the program and examine some debugging features of the Altera Monitor Program

56. Application Code (/exercise5/fpga_gpio.c)
Read switches and display on LEDs and 7-Segs
int main(void)(
volatile int * LEDs = (int *) 0xFF200000;
volatile int * HEX3_HEX0 = (int *) 0xFF200020;
volatile int * SW_switch = (int *) 0xFF200040;
int hex_conversions[16] = {0x3F, ..., 0x71};
while(1) {
int value = *SW_switch;
*LEDs = value;
int first_digit = value & 0xF;
int second_digit = (value >> 4) & 0xF;
int third_digit = (value >> 8) & 0xF;
int hex_value = hex_conversions[first_digit];
hex_value |= hex_conversions[second_digit] << 8;
hex_value |= hex_conversions[third_digit] << 16;
*HEX3_HEX0 = hex_value; }

57. Application Code (/exercise5/fpga_gpio.c)
Read switches and display on LEDs and 7-Segs
int main(void)(
volatile int * LEDs = (int *) 0xFF200000;
volatile int * HEX3_HEX0 = (int *) 0xFF200020;
volatile int * SW_switch = (int *) 0xFF200040;
int hex_conversions[16] = {0x3F, ..., 0x71};
while(1) {
int value = *SW_switch;
*LEDs = value;
int first_digit = value & 0xF;
int second_digit = (value >> 4) & 0xF;
int third_digit = (value >> 8) & 0xF;
int hex_value = hex_conversions[first_digit];
hex_value |= hex_conversions[second_digit] << 8;
hex_value |= hex_conversions[third_digit] << 16;
*HEX3_HEX0 = hex_value; }

58. Application Code (/exercise5/fpga_gpio.c)
Read switches and display on LEDs and 7-Segs
int main(void)(
volatile int * LEDs = (int *) 0xFF200000;
volatile int * HEX3_HEX0 = (int *) 0xFF200020;
volatile int * SW_switch = (int *) 0xFF200040;
int hex_conversions[16] = {0x3F, ..., 0x71};
while(1) {
int value = *SW_switch;
*LEDs = value;
int first_digit = value & 0xF;
int second_digit = (value >> 4) & 0xF;
int third_digit = (value >> 8) & 0xF;
int hex_value = hex_conversions[first_digit];
hex_value |= hex_conversions[second_digit] << 8;
hex_value |= hex_conversions[third_digit] << 16;
*HEX3_HEX0 = hex_value; }

59. Program Behaviour

60. Program Behaviour

61. Step 1: Start Altera Monitor Program

62. Step 2: Create a New Project
Sets up the Altera Monitor Program
Select files to work with
Specify target system

63. Step 2.1: Specify name, directory and architecture

64. Step 2.2: Select a Custom System

65. Step 2.3: Select Program Type

66. Step 2.4: Add Source File

67. Step 2.5: Set Board Connection and Select Processor

68. Step 2.6: Leave Default Memory Settings

69. Step 3: Program the FPGA with the Custom System

70. Step 4: Compile and Load
Compile your C language program
Load the compiled code into the memory on the DE1-SoC board

71. Step 5: Examine the Window Contents

72. Step 5: Examine the Window Contents
Disassembly

73. Step 5: Examine the Window Contents
Registers

74. Step 5: Examine the Window Contents
Info & Error Msgs

75. Step 5: Examine the Window Contents
Terminal

76. Step 6: Run the Program and Toggle Switches on Board

77. Step 7: Pause the Processor

78. Step 8: Go to 0xff200000 in Memory Window3 2 1

79. Step 9: Read PIO Registers (Right Click)

80. Step 9: Examine Values

81. Step 10: Alter the Red LED PIO Register (Double Click)

82. Step 11: Test Other Features
Single Step

83. Step 11: Test Other Features
Breakpoints

84. Step 11: Test Other Features
Restart Program

85. Step 12: Disconnect

86. Please read the instructions at
Hands-On Session
Please read the instructions at
“/exercise5/instructions.pdf”
If you did not finish exercise 4, use the solutions in /exercise5/exercise4_solutions/
We will be walking around to help with any issues

87. Where did we go from here?
Summary of Tutorial #2
Learned how to
Use Qsys to build a system
Compile a Qsys system in Quartus
Write and compile applications for an ARM-based embedded system using Altera Monitor Program
Where did we go from here?
Tutorials:
Introduction to the Altera Qsys System Integration Tool
Making Qsys Components
Altera Monitor Program Tutorial for ARM
Embedded systems laboratory exercises
Heres what we learned, let me talk about materials you can use for your students