1. M.N Minard Trigger Validation Board Status Cyril Drancourt, Pierre-Yves David,Victor Coco, M.N Minard - Production status - TVB tests on Cryo side

2. M.N Minard Production status - 35 cards tested in lab with version 5.3 (14/09/07) -V5.3 change clock treatment - 14 functionning on Cryo side - 14 ready to equip side A - 3 spares OK - 1 TVB OK no mezzanine - 3 TVB cards under study (ram cannot be read) - 3 mezzanines with problem

3. M.N Minard Cryo Side Installation - 14 TVB cards installed since 24 of September - Tested in situ - Scan of delay chip for ECAL entries - Scan of delay chip for HCAL entries - Scan of delay chip for PS entries ( in progress) V4.1 September ns Allowed window width V5.3 Used

4. M.N Minard Comparison labo / pit - Ecal channels - For the processing at the pit some channels are not used -> wider range

5. M.N Minard Delay Chip range allowed ns HCALEPPIHCALEPPI Rising edge Transfert trough mezzanine Falling edge Allowed range Hcal EPPI ns Rising front preferred for EPPI FPGA

6. M.N Minard Scan HCAL inputs to TVB 2 patterns to test all address and energy bits _ Rising front: 8 delay chip position forbidden for each front -> always a solution Same test being done with PS. To adjust overall synchro need to adjust BCID from the same ODIN

7. M.N Minard PVSS for TVB - Basic Version developped & installed by Stéphane T. is working. -Load TVB register. -Load LUT from specific file. Solution to be improved - More panels to be developped ( read & diplay the spy memories)