1. x86 (32-bit) Paging Reference –text: Tanenbaum ch.4.3 Reference on Win2K memory management –text: Tanenbaum ch. 11.5.3

2. x86 Multilevel Paging Page table #0 Page table #1 Page table #1023 0 1 4095 Page Table Directory Page Which page table? Which page? What offset? 32-bit virtual address 10 bits 12 bits Page #0 Page #1 Page #1023 Page Table 12 bits 20 bits 32-bit physical address

3. x86 Page Table Entry Important bits –V: bit =1, valid page table entry –W: bit=1, writing to page permitted –U: bit =1, page is accessible in user mode –A: bit =1, page has been accessed –D: bit =1, page is dirty(has been modified) VWU Wt CADLGNot usedPage frame Bit 12-31 0 1 23 4 5 6 7 8 9-11

4. SAPC Memory Management Paging is turned on 4M(0x3f ffff) byte memory fits into 1 page table 1 Page Table(PT) at virtual address 0x52000 (in the Tutor area) has –1024 Page Table Entries(PTE) which point to 1024 pages Each page has 4096 memory locations Total address 1x1024x4096= 4M

5. SAPC Memory Management (cont’d) Tutor> mdd 52000 0005200000000007000010070000200700003007 PTE0 PTE1 PTE2 PTE3 Page Table –Page 0 -> Page frame 0 –Page 1 -> Page frame 1 –and so on Important Bits for PTE0 –D=0; A=0; U=1; W=1; V =1 Page frame number Important bits Identity paging: VA = PA for every address 0 to 0x 3f ffff. Paging is turned on, memory is being used as if paging is not on.

6. Important Bits For PTE0 D=0 :page 0 has not been modified A=0 : page 0 has not been accessed U=1 :page 0 is accessed in user mode W=1:page 0 permits writes to the page V =1:page 0 is valid See the bits in motion Tutor> md 400 ---------> PTE0: A=1 Tutor> ms a00 66 ------> PTE0: A=1, D=1 Memory display in bytes

7. Experiment with Paging Currently we have identity paging page 0 -> page frame 0 page 1 -> page frame 1 and so on We can modify the page table to: page 0 -> page frame 2 by changing PTE0 page 1 -> page frame 1 page 2 -> page frame 6 by changing PTE2 Modify using Tutor Tutor> ms 52000 00002007 Tutor> ms 52008 00006007 Tutor>mdd 52000 0005200000002007 00001007 00006007 Memory display in double words

8. Instruction Example mov %eax, 0 Operand address 0 is a VA Use the last page table, page 0 -> page frame 2 MMU will map VA 0 into physical address 0x2000

9. Page Faults Refer to the virtual address -> physical address mapping example: What happens to page 6? Access to page 6 (address 0x6000-6fff) will cause a page fault Page fault is a trap to OS and the OS decides what to do May access the disk to read the executable file for another page of code. Fill in the page table and set the page’s V bit =1. This causes the CPU to re-execute the instruction. This time will be successful because V bit=1.

10. Page Fault Handling Most instruction execution does not cause page faults and does not involve the OS The OS gets involved only occasionally when a new page is referenced for the first time. A program image starts out with only a few pages of memory and page faults notify the OS of the needs of additional program. The strategy that pages are loaded only on demand, not in advance, is called demand paging.

11. Multiple Page Tables The SAPC only uses one page table handling 4M of VA space A real 32-bit system addresses 4G of memory space. It takes 1024 page tables grouped together in a page directory(PD). The physical address of PD is stored in CPU’s CR3 register. The Page Directory Entries(PDE) have the same format as the Page Table Entries(PTE) except that the D bit is not in use

12. Page Directory Need overhead memory 1024 x 32 bits (for PDEs) + 1024 x 1024 x 32 bits (for PTEs) = 1025x 4K=4M bytes for a 4G program For a small program(~ 3PTs: 1 PT for code +data, 1 PT for stack, 1PT for C Library and DLLs), too much overhead Small program uses the V-bit in PDE to mark only those PTs that are in use It uses 3 PTs and 1PD (1024 x 3 x32 + 1024 x 32 bits) ~16K bytes

13. Virtual Address -> Physical Address Example VA = 0x12345678 = 0001 0010 0011 0100 0101 0110 0111 1000 MMU would access PDE 0x48 to find the location of PT. MMU would access PTE 0x345 to find the physical page. Put together the physical page number and offset to form the physical address PDE = 0x48PTE = 0x345offset = 0x678