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Penn ESE370 Fall2011 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 4: September 14, 2011 Gates from Transistors.

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Presentation on theme: "Penn ESE370 Fall2011 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 4: September 14, 2011 Gates from Transistors."— Presentation transcript:

1 Penn ESE370 Fall2011 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 4: September 14, 2011 Gates from Transistors

2 Previously Simplified models for reasoning about transistor circuits –Zeroth-order –First-order Penn ESE370 Fall2011 -- DeHon 2

3 Today How to construct static CMOS gates Penn ESE370 Fall2011 -- DeHon 3

4 Outline Circuit understanding (preclass) Static CMOS –Structure –Inverter –Construct gate –Inverting –Cascading Penn ESE370 Fall2011 -- DeHon 4

5 What gate? Penn ESE370 Fall2011 -- DeHon 5

6 What function? Penn ESE370 Fall2011 -- DeHon 6

7 DeMorgan’s Law /f = a + b What is f? Penn ESE370 Fall2011 -- DeHon 7

8 What function? Penn ESE370 Fall2011 -- DeHon 8

9 Static CMOS Gate Penn ESE370 Fall2011 -- DeHon 9

10 Static CMOS Gate Structure Penn ESE370 Fall2011 -- DeHon 10

11 Static CMOS Gate Structure Penn ESE370 Fall2011 -- DeHon 11

12 Static CMOS Gate Structure Drives rail-to-rail (output is Vdd or Gnd) Inputs connects to gates  load is capacitive Once charge capacitive output, doesn’t use energy –(first order) Output actively driven Penn ESE370 Fall2011 -- DeHon 12

13 Inverter Out = /in Penn ESE370 Fall2011 -- DeHon 13

14 Inverter Penn ESE370 Fall2011 -- DeHon 14

15 Gate Design Example Penn ESE370 Fall2011 -- DeHon 15

16 Gate Design Design gate to perform: f=(/a+/b)*/c Penn ESE370 Fall2011 -- DeHon 16

17 f=(/a+/b)*/c Strategy: 1.Use static CMOS structure 2.Design PMOS pullup for f 3.Use DeMorgan’s Law to determine /f 4.Design NMOS pulldown for /f Penn ESE370 Fall2011 -- DeHon 17

18 f=(/a+/b)*/c PMOS Pullup for f? Penn ESE370 Fall2011 -- DeHon 18

19 f=(/a+/b)*/c Use DeMorgan’s Law to determine /f. What is /f ? Penn ESE370 Fall2011 -- DeHon 19

20 f=(/a+/b)*/c NMOS Pulldown for /f? Penn ESE370 Fall2011 -- DeHon 20

21 f=(/a+/b)*/c Penn ESE370 Fall2011 -- DeHon 21 a c b

22 Inverting Gate Penn ESE370 Fall2011 -- DeHon 22

23 Inverting Stage Each stage of Static CMOS gate is inverting Penn ESE370 Fall2011 -- DeHon 23

24 Why not? Penn ESE370 Fall2011 -- DeHon 24

25 Source/Drain Reminder Source is: –Most negative terminal NMOS source of the electrons –Most positive terminal PMOS Source of holes Penn ESE370 Fall2011 -- DeHon 25

26 Source Drain Annotation Penn ESE370 Fall2011 -- DeHon 26 S S S S S S D D D D D D

27 Static CMOS Source/Drains With PMOS on top, NMOS on bottom –PMOS source always at top (near Vdd) –NMOS source always at bottom (near Gnd) Penn ESE370 Fall2011 -- DeHon 27

28 Why not buffer? Penn ESE370 Fall2011 -- DeHon 28 D D S S

29 Input at 0V Vgs NMOS? Vgs PMOS? Output voltage? Penn ESE370 Fall2011 -- DeHon 29 D D S S

30 D D S S Input at Vdd Vgs NMOS? Vgs PMOS? Output voltage? Penn ESE370 Fall2011 -- DeHon 30

31 Behavior Roundup VinInitial VoutFinal Vout 0Vout<0.3Vout (unchanged) 0Vout>0.30.3 1Vout<0.70.7 1Vout>0.7Vout (unchanged) Penn ESE370 Fall2011 -- DeHon 31

32 Why not buffer? Output signal not drive to rails One threshold voltage away True any time use PMOS/NMOS on “wrong” side What’s wrong with it not driving to rails? Penn ESE370 Fall2011 -- DeHon 32

33 How do we buffer? Penn ESE370 Fall2011 -- DeHon 33

34 How implement OR? Penn ESE370 Fall2011 -- DeHon 34

35 Cascading Stages Penn ESE370 Fall2011 -- DeHon 35

36 Stages Can always cascade “stages” to build more complex gates Could simply build nor2 at circuit level and assemble arbitrary logic by combining – universality –but may not be smallest/fastest/least power Penn ESE370 Fall2011 -- DeHon 36

37 Implement: f=a*/b Pullup? Pulldown? Penn ESE370 Fall2011 -- DeHon 37

38 f=a*/b Penn ESE370 Fall2011 -- DeHon 38

39 Admin Friday in Detkin (RCA) Lab –Note homework 1 (due Friday) to design gates before lab –Please read through HW2, Lab1 details –Bring USB drive with you to lab on Friday to store waveforms Penn ESE370 Fall2011 -- DeHon 39

40 Big Idea Systematic construction of any gate from transistors 1.Use static CMOS structure 2.Design PMOS pullup for f 3.Use DeMorgan’s Law to determine /f 4.Design NMOS pulldown for /f Penn ESE370 Fall2011 -- DeHon 40

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