2. ICC Module 3 Lesson 2 – Memory Hierarchies 1 / 14 © 2015 Ph. Janson Information, Computing & Communication Memory Hierarchies – Clip 5 – Reading School of Computer Science & Communications B. Falsafi (charts), Ph. Janson (commentary)

3. ICC Module 3 Lesson 2 – Memory Hierarchies 2 / 14 © 2015 Ph. Janson Outline ►Clip 1 – TechnologiesClip 1 ►Clip 2 – ConceptClip 2 ►Clip 3 – PrincipleClip 3 ►Clip 4 – ImplementationClip 4 ►Clip 5 – Reading memoryClip 5 ►Clip 6 – Writing memoryClip 6 ►Clip 7 – Cache management – the Least Recently Used algorithmClip 7 ►Clip 8 – A simulated exampleClip 8 ►Clip 9 – LocalityClip 9 First clipPrevious clipNext clip

4. ICC Module 3 Lesson 2 – Memory Hierarchies 3 / 14 © 2015 Ph. Janson 6 questions follow ►Q1: how does the processor read a word ?  Q1.a: when the word is in the cache ?  Q1.b: when the word is out of the cache ? ►Q2: how does the processor write a word ?  Q2.a: when the word is in the cache ?  Q2.b: when the word is out of the cache ? ►Q3: what happens when the cache is full ? ►Q4: what happens when a cache block to be replaced has been modified ? Cache 23 17 90 104 8 8 Main memory 40 23 0 4 8 12 45 17 100 90 16 104 Processor

5. ICC Module 3 Lesson 2 – Memory Hierarchies 4 / 14 © 2015 Ph. Janson Q1.a: how does the processor read a word when it is in cache? 1. The processor sends a read command to the cache Cache 23 17 90 104 8 8 Main memory 40 23 0 4 8 12 45 17 100 90 16 104 Processor Read @ address 9

6. ICC Module 3 Lesson 2 – Memory Hierarchies 5 / 14 © 2015 Ph. Janson Q1.a: how does the processor read a word when it is in cache? 2. The cache sees that the requested word is present Cache 23 17 90 104 8 8 Main memory 40 23 0 4 8 12 45 17 100 90 16 104 Processor

7. ICC Module 3 Lesson 2 – Memory Hierarchies 6 / 14 © 2015 Ph. Janson Q1.a: how does the processor read a word when it is in cache? 3. The cache sends back the content of the requested word Cache 23 17 90 104 8 8 Main memory 40 23 0 4 8 12 45 17 100 90 16 104 Processor 17

8. ICC Module 3 Lesson 2 – Memory Hierarchies 7 / 14 © 2015 Ph. Janson 5 questions remain ►Q1: how does the processor read a word ?  Q1.a: when the word is in the cache ?  Q1.b: when the word is out of the cache ? ►Q2: how does the processor write a word ?  Q2.a: when the word is in the cache ?  Q2.b: when the word is out of the cache ? ►Q3: what happens when the cache is full ? ►Q4: what happens when a cache block to be replaced has been modified ? Cache 23 17 90 104 8 8 Main memory 40 23 0 4 8 12 45 17 100 90 16 104 Processor

9. ICC Module 3 Lesson 2 – Memory Hierarchies 8 / 14 © 2015 Ph. Janson Q1.b: how does the processor read a word out of cache? 1. The processor sends a read command to the cache Cache 23 17 90 104 8 8 Main memory 40 23 0 4 8 12 45 17 100 90 16 104 Processor Read @ address 2

10. ICC Module 3 Lesson 2 – Memory Hierarchies 9 / 14 © 2015 Ph. Janson Q1.b: how does the processor read a word out of cache? 2. The cache sees that the requested word is NOT present Cache 23 17 90 104 8 8 Main memory 40 23 0 4 8 12 45 17 100 90 16 104 Processor

11. ICC Module 3 Lesson 2 – Memory Hierarchies 10 / 14 © 2015 Ph. Janson Q1.b: how does the processor read a word out of cache? 3. Absence of the word causes a so-called “cache (de)fault” Cache 23 17 90 104 8 8 Main memory 40 23 0 4 8 12 45 17 100 90 16 104 Processor

12. ICC Module 3 Lesson 2 – Memory Hierarchies 11 / 14 © 2015 Ph. Janson Q1.b: how does the processor read a word out of cache? 4. The cache sends the main memory a command to read the block containing the requested word Cache 23 17 90 104 8 8 Main memory 40 23 0 4 8 12 45 17 100 90 16 104 Processor Read block 0

13. ICC Module 3 Lesson 2 – Memory Hierarchies 12 / 14 © 2015 Ph. Janson Q1.b: how does the processor read a word out of cache? 5. The main memory sends back the requested block Cache 23 17 90 104 8 8 Main memory 40 23 0 4 8 12 45 17 100 90 16 104 Processor 40 45 100 16

14. ICC Module 3 Lesson 2 – Memory Hierarchies 13 / 14 © 2015 Ph. Janson Q1.b: how does the processor read a word out of cache? 6. The cache saves the received block and its main memory address Cache 40 23 45 17 100 90 16 104 0 0 8 8 Main memory 40 23 0 4 8 12 45 17 100 90 16 104 Processor

15. ICC Module 3 Lesson 2 – Memory Hierarchies 14 / 14 © 2015 Ph. Janson Q1.b: how does the processor read a word out of cache? 7. The cache sends the requested word back to the processor Cache 40 23 45 17 100 90 16 104 0 0 8 8 Main memory 40 23 0 4 8 12 45 17 100 90 16 104 Processor 100