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CS-EE 481 Spring 2005 1 University of Portland School of Engineering Project Golden Mantle CMOS 8-Bit Analog-to-Digital Converter Team T Travis Tompkins.

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Presentation on theme: "CS-EE 481 Spring 2005 1 University of Portland School of Engineering Project Golden Mantle CMOS 8-Bit Analog-to-Digital Converter Team T Travis Tompkins."— Presentation transcript:

1 CS-EE 481 Spring 2005 1 University of Portland School of Engineering Project Golden Mantle CMOS 8-Bit Analog-to-Digital Converter Team T Travis Tompkins K Aaron Krizek O Scott Ostrow Advisor Dr. Joe Hoffbeck Dr. Peter Osterberg Industry Representative Mr. Howard Voorheis

2 CS-EE 481 Spring 2005 2 University of Portland School of Engineering Overview Introduction (again) Accomplishments Plans Issues/Concerns Conclusions

3 CS-EE 481 Spring 2005 3 University of Portland School of Engineering Introduction 8-Bit Analog-to-Digital Converter “Tracking” ADC Architecture

4 CS-EE 481 Spring 2005 4 University of Portland School of Engineering Introduction continued Continuous time signal “coded” into stream of binary numbers Key component in communication systems - Cell Phones, Satellite Transmission, Digital Signal Processing

5 CS-EE 481 Spring 2005 5 University of Portland School of Engineering Accomplishments Project Plan Approval Meeting with Industry Representative Finished Digital Chip Logic Design Finished *.tpr file

6 CS-EE 481 Spring 2005 6 University of Portland School of Engineering MOSIS CHIP Bonding pads: 40 Layout size: 2200 x 2200 microns; Area: 4.836 sq mm Packaging: DIP40 Maximum die size: 7366 x 7366

7 CS-EE 481 Spring 2005 7 University of Portland School of Engineering Bill of Materials?

8 CS-EE 481 Spring 2005 8 University of Portland School of Engineering Plans Design Release –With Approval Meeting Order Analog Parts

9 CS-EE 481 Spring 2005 9 University of Portland School of Engineering Milestone Table NumberDescriptionOriginalPreviousPresent 1Product Pre-Approval09/08/04 2Functional Spec Approval v1.0 (Approval Meeting) 10/08/04 10/11/04 3Project Plan Approval v1.0 (Approval Meeting) 11/05/0411/08/04 6*.tpr File Completion11/24/04 7Off-chip Components Ordered12/03/04 8Design Release (Approval Meeting) 12/06/04 12/15/04 9TOP’s Approval v1.0 (Approval Meeting) 02/11/05 10Chip Received From MOSIS03/15/05* 11Prototype Release04/08/05 12Founder’s Day Presentation04/12/05 13Final Report04/22/05

10 CS-EE 481 Spring 2005 10 University of Portland School of Engineering Concerns/Issues Ordering Correct Parts (for Spring) Budgeting Hoping that *.tpr file was correct

11 CS-EE 481 Spring 2005 11 University of Portland School of Engineering Conclusions Introduction Accomplishments Plans Issues/Concerns

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