1. Example 1 Program the divisor Latch for 300 baud. Assume Xin=1.8432MHz The Base Address: 0x3F8 0RX_TX / Divisor.low 1IER: Interrupt Enable Reg. / Divisor.high 2IIR: Interrupt Identification Reg. 3LCR: Line Control Reg. 4MCR: Modem Control Reg. 5LSR: Line Status Reg. 6MSR: Modem Status Reg. 7- 300*384=115200 115200*16=1843200

2. Example 2 Program the divisor Latch for 2400 baud. Assume Xin=1.8432MHz The Base Address: 0x3F8 2400*48=115200 115200*16=1843200

3. Example 3 Program 8250 for 2400 baud, 8 data bit, even parity and 1 stop bit. Assume Xin=1.8432MHz The Base Address: 0x3F8 MOVAL,80H; Accessing DLAB MOVDX,3FBH;Line Control Register Address OUTDX,AL MOVAX,48;baud=2400 115200:48=2400 MOVDX,3F8H;Low byte of Divisor OUTDX,AL MOVAL,AH INCDX OUTDX,AL MOVAL,00011011; DLAB,Break,Even,1 stop, 8 data MOVDX,3FBH;LCR OUTDX,AL

4. Synchronous Serial Communication Introduction to USART Intel 8251

5. Serial Data Transfer  Asynchronous v.s. Synchronous — Asynchronous transfer does not require clock signal. However, it transfers extra bits (start bits and stop bits) during data communication — Synchronous transfer does not transfer extra bits. However, it requires clock signal Frame Start bit B0B1B2B3B4B5B6 Parity Stop bits Asynchronous Data transfer Synchronous Data transfer clk data B0B1B2B3B4B5 data

6. (a) Serial data transmitted at the proper rate. (b) The data rate is too fast. (c) The data rate is too slow.

7. Serial Frame (Synchronous) Bit 7 0 1 2 3 4 5 6 7 0 No start or stop bits, timing synchronized with special ASCII characters (SYN) Time

8. Synchronous Protocols

9. CRC In SDLC: G(X) = x**16 + x**12 + x**5 + 1

11. 8251 Block Diagram

12. 8251 Registers

13. Mode Register

14. Mode Instruction (Asynchronous)

15. Mode Instruction (Synchronous)

16. Command Register

17. Status Register

18. 8251 Timing

19. 8251 USART Interface A7 A6 A5 A4 A3 A2 A1 IO/M D[7:0] RD WR A0C/D CLK TxC RxC TxD RxD 8251 RS232

20. Programming 8251  8251 mode register 76543210 Mode register Number of Stop bits 00: invalid 01: 1 bit 10: 1.5 bits 11: 2 bits Parity 0: odd 1: even Parity enable 0: disable 1: enable Character length 00: 5 bits 01: 6 bits 10: 7 bits 11: 8 bits Baud Rate 00: Syn. Mode 01: x1 clock 10: x16 clock 11: x64 clock

21. Programming 8251  8251 command register EHIRRTSERSBRKRxEDTRTxE command register TxE:transmit enable DTR:data terminal ready RxE:receiver enable SBPRK:send break character ER:error reset RTS:request to send IR:internal reset EH:enter hunt mode

22. Programming 8251  8251 status register DSR SYNDE TFEOEPE TxEMPTY RxRDYTxRDY status register TxRDY:transmit ready RxRDY:receiver ready TxEMPTY:transmitter empty PE:parity error OE:overrun error FE:framing error SYNDET:sync. character detected DSR:data set ready

23. Simple Serial I/O Procedures  Read start Check RxRDY Is it logic 1? Read data register* end Yes No * This clears RxRDY  Write start Check TxRDY Is it logic 1? Write data register* end Yes No * This clears TxRDY

24. 8251 Reset Sequence write three successive zeros to control address to assure writing a reset to the command register. write command 40h to reset (reset chip) – After the reset, 8251 expects mode settings write the mode settings to control address – There after 8251 needs command settings. write command for command settings.

26. 8251 Coding MOVDX,309h MOVAL,0 OUTDX,AL MOVAL,40h OUTDX,AL MOVAL,4Eh OUTDX,AL MOVAL,33h OUTDX,AL Main: MOVDX,300h INAL,DX MOVAH,AL MOVDX,309h Wait INAL,DX ANDAL,01 JZWait MOVAL,AH MOVDX,308h OUTDX,AL JMPMain