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What’s New in Xilinx Ready-to-use solutions. Key New Features of the Foundation Series 1.5/1.5i Release  New device support  Integrated design environment.

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Presentation on theme: "What’s New in Xilinx Ready-to-use solutions. Key New Features of the Foundation Series 1.5/1.5i Release  New device support  Integrated design environment."— Presentation transcript:

1 What’s New in Xilinx Ready-to-use solutions

2 Key New Features of the Foundation Series 1.5/1.5i Release  New device support  Integrated design environment with advanced design flow automation control  Full verilog support  “Point” tool productivity enhancements Design tools Synthesis Implementation tools  Web-enabled Design Features

3 Foundation Series 1.5 New Device Support  XC9500 XL - true ISP, 3.3V cplds  Spartan XL - no compromise architecture at 3.3V  Virtex - system level programmable logic  Continued device support for: Xc3000x, xc3100x, XC4KX, XC5200, XC9500, spartan

4 Foundation Series 1.5 Integrated Design Environment  Synopsys FPGA Express 2.1 directly embedded within foundation PCM  Xilinx implementation tools with A.K.A. Speed Technology embedded within PCM  Aldec’s Active-VHDL direct push button interface (purchased as an option from Aldec)

5 Foundation Series 1.5 Full Verilog Support  State Editor Now Generates Verilog HDL  Full HDL Editor Support Color Coding Language Assistant Verilog Templates Verilog HDL Syntax Checking  Schematic Editor Supports Verilog Modules (Macros)  Verilog Source Code Debugging via MTI* * Evaluation copies of ModelSim are included with all Foundation Series HDL packages. Licensed, Sold, and Supported separately by Model Technology Inc.

6  Synthesis (FPGA Express)  Implementation Tools (A.K.A. Speed Technology)  Schematic Editor  HDL Editor  Gate Level Simulator Foundation Series 1.5 Point Tool Enhancements

7 Point Tool Enhancements Express Synthesis  Embedded with foundation series PCM  Virtex specific optimization  Addition of important VHDL ‘93 constructs End keyword-component keyword Is keyword-labels on assignments T’image(x)-block in generate Alias keyword-array slices with others  Addition of other HDL constructs Rising_edge / falling_edge ‘Else Hex, octal and binary for std_logic_vectors

8  State machine synthesis options FSM Encoding Style One Hot Binary FSM Extraction Method Safest (all possible states) Smallest (defined states only) Point Tool Enhancements Express Synthesis

9  Embedded within foundation series PCM  A.K.A. Speed technology Device floorplanner Xilinx constraints editor New timespecs Temperature pro-rating Min-delays K-paths timing analysis algorithm Point Tool Enhancements Implementation Tools

10 Point Tool Enhancements Schematic Editor  Re-implemented bus behavior Complex buses Bus editing now similar to wire editing  Enhanced wire behavior Selection, deletion Autowiring / rubberbanding  Local menus (e.g., right-click > hierarchy push, copy/paste, symbol properties, etc.)  “SC symbols” dialog box enhanced - project components separated from unified library comps

11 Point Tool Enhancements Schematic Editor (continued)  “Replace symbol” option now has a drop-down selector from which to pick new symbol  Symbol attributes can now be moved directly (no need to bring up properties dialog)  Multi-level undo (5 levels)  Copy/paste enhancement: objects to be pasted are visible as copy buffer is moved around on the schematic  Enhanced CORE generator 1.5 interface (i.E., Symbol generation)

12 Point Tool Enhancements HDL Editor  New “insert file” item in edit menu Provides easy method for insertion of logiblox and CORE generator created instantiation templates  Verilog syntax checking, color-coding, language templates, schematic flow macro synthesis  VHDL language assistant templates updated to be express compliant

13 Point Tool Enhancements Gate-Level Simulator  Virtex LUT support Some limitations at first release; may be addressed in performance pack Typical user will want to use behavioral simulator anyway  Memory allocation tuning to support larger netlists  Signal selection dialog “search” feature enhanced

14 Point Tool Enhancements Gate-Level Simulator (continued)  New simulation script wizard Invoke at script editor start-up or Invoke from script editor’s tools menu  “Enable global netlist analysis” feature May speed up simulation if disabled Project-specific (not always needed)

15 Foundation Series 1.5 Web-enabled Design Features  Integrated into Project Manager  Instant Access to http://support.xilinx.com  Netscape and MS Explorer compatible News Bulletins Searchable Knowledge Base (includes agent reports) Designer Tools & Services


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