1. Copyright Agrawal, 2007Lectures 5, 6, 7: Power Analysis1 CSV881: Low-Power Design Gate-Level Power Analysis Vishwani D. Agrawal James J. Danaher Professor Dept. of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 vagrawal@eng.auburn.edu http://www.eng.auburn.edu/~vagrawal

2. Copyright Agrawal, 2007Lectures 5, 6, 7: Power Analysis2 Power Analysis Motivation: Motivation: Specification Specification Optimization Optimization Reliability Reliability Applications Applications Design analysis and optimization Design analysis and optimization Physical design Physical design Packaging Packaging Test Test

3. Copyright Agrawal, 2007Lectures 5, 6, 7: Power Analysis3 Abstraction, Complexity, Accuracy Abstraction level Computing resources Analysis accuracy AlgorithmLeastWorst Software and system Hardware behavior Register transfer Logic Circuit DeviceMostBest

4. Copyright Agrawal, 2007Lectures 5, 6, 7: Power Analysis4 Spice Circuit/device level analysis Circuit/device level analysis Circuit modeled as network of transistors, capacitors, resistors and voltage/current sources. Circuit modeled as network of transistors, capacitors, resistors and voltage/current sources. Node current equations using Kirchhoff’s current law. Node current equations using Kirchhoff’s current law. Average and instantaneous power computed from supply voltage and device current. Average and instantaneous power computed from supply voltage and device current. Analysis is accurate but expensive Analysis is accurate but expensive Used to characterize parts of a larger circuit. Used to characterize parts of a larger circuit. Original references: Original references: L. W. Nagel and D. O. Pederson, “SPICE – Simulation Program With Integrated Circuit Emphasis,” Memo ERL-M382, EECS Dept., University of California, Berkeley, Apr. 1973. L. W. Nagel and D. O. Pederson, “SPICE – Simulation Program With Integrated Circuit Emphasis,” Memo ERL-M382, EECS Dept., University of California, Berkeley, Apr. 1973. L. W. Nagel, SPICE 2, A Computer program to Simulate Semiconductor Circuits, PhD Dissertation, University of California, Berkeley, May 1975. L. W. Nagel, SPICE 2, A Computer program to Simulate Semiconductor Circuits, PhD Dissertation, University of California, Berkeley, May 1975.

5. Copyright Agrawal, 2007Lectures 5, 6, 7: Power Analysis5 CaCa Logic Model of MOS Circuit CcCc CbCb V DD a b c pMOS FETs nMOS FETs C a, C b, C c and C d are node capacitances DcDc DaDa c a b D a and D b are interconnect or propagation delays D c is inertial delay of gate DbDb CdCd

6. Copyright Agrawal, 2007Lectures 5, 6, 7: Power Analysis6 Spice Characterization of a 2-Input NAND Gate Input data pattern Delay (ps) Dynamic energy (pJ) a = b = 0 → 1 a = b = 0 → 1691.55 a = 1, b = 0 → 1 a = 1, b = 0 → 1621.67 a = 0 → 1, b = 1 a = 0 → 1, b = 1501.72 a = b = 1 → 0 351.82 a = 1, b = 1 → 0 761.39 a = 1 → 0, b = 1 571.94

7. Copyright Agrawal, 2007Lectures 5, 6, 7: Power Analysis7 Spice Characterization (Cont.) Input data pattern Static power (pW) a = b = 0 a = b = 05.05 a = 0, b = 1 a = 0, b = 113.1 a = 1, b = 0 5.10 a = b = 1 28.5

8. Copyright Agrawal, 2007Lectures 5, 6, 7: Power Analysis8 Switch-Level Partitioning Circuit partitioned into channel-connected components for Spice characterization. Circuit partitioned into channel-connected components for Spice characterization. Reference: R. E. Bryant, “A Switch-Level Model and Simulator for MOS Digital Systems,” IEEE Trans. Computers, vol. C-33, no. 2, pp. 160-177, Feb. 1984. Reference: R. E. Bryant, “A Switch-Level Model and Simulator for MOS Digital Systems,” IEEE Trans. Computers, vol. C-33, no. 2, pp. 160-177, Feb. 1984. G1G1 G2G2 G3G3 Internal switching nodes not seen by logic simulator

9. Copyright Agrawal, 2007Lectures 5, 6, 7: Power Analysis9 Delay and Discrete-Event Simulation (NAND gate) b a c (CMOS) Time units 0 5 c (zero delay) c (unit delay) c (multiple delay) c (minmax delay) Inputs Logic simulation min =2, max =5 rise=5, fall=5 Transient region Unknown (X) X

10. Copyright Agrawal, 2007Lectures 5, 6, 7: Power Analysis10 Event-Driven Simulation Example 2 2 4 2 a =1 b =1 c =1→0 d = 0 e =1 f =0 g =1 Time, t 0 4 8 g t = 0 1 2 3 4 5 6 7 8 Scheduled events c = 0 d = 1, e = 0 g = 0 f = 1 g = 1 Activity list d, e f, g g Time stack

11. Copyright Agrawal, 2007Lectures 5, 6, 7: Power Analysis11 Time Wheel (Circular Stack) t=0 1 2 3 4 5 6 7 max Current time pointer Event link-list

12. Copyright Agrawal, 2007Lectures 5, 6, 7: Power Analysis12 Gate-Level Power Analysis Pre-simulation analysis: Pre-simulation analysis: Partition circuit into channel connected components. Partition circuit into channel connected components. Determine node capacitances from layout analysis (accurate) or from wire-load model* (approximate). Determine node capacitances from layout analysis (accurate) or from wire-load model* (approximate). Determine dynamic and static power from Spice for each gate. Determine dynamic and static power from Spice for each gate. Determine gate delays using Spice or Elmore delay model. Determine gate delays using Spice or Elmore delay model. * Wire-load model estimates capacitance of a net by its pin-count. See Yeap, p. 39.

13. Copyright Agrawal, 2007Lectures 5, 6, 7: Power Analysis13 Elmore Delay Model W. Elmore, “The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers,” J. Appl. Phys., vol. 19, no.1, pp. 55-63, Jan. 1948. W. Elmore, “The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers,” J. Appl. Phys., vol. 19, no.1, pp. 55-63, Jan. 1948. s 1 2 3 4 5 R1 R2 R3 R4 R5 C1 C2 C3 C5 C4 Shared resistance: R45 = R1 + R3 R15 = R1 R34 = R1 + R3

14. Copyright Agrawal, 2007Lectures 5, 6, 7: Power Analysis14 Elmore Delay Formula N Delay at node k= 0.69Σ Cj × Rjk j=1 where N = number of capacitive nodes in the network Example: Delay at node 5= 0.69[R1 C1 + R1 C2 + (R1+R3)C3 + (R1+R3)C4 + (R1+R3+R5)C5]

15. Copyright Agrawal, 2007Lectures 5, 6, 7: Power Analysis15 Gate-Level Power Analysis (Cont.) Run discrete-event (event-driven) logic simulation with a set of input vectors. Run discrete-event (event-driven) logic simulation with a set of input vectors. Monitor the toggle count of each net and obtain capacitive component of power dissipation: Monitor the toggle count of each net and obtain capacitive component of power dissipation: P cap = Σ C k V 2 f all nodes k all nodes k Where: Where: C k is the total node capacitance being switched, as determined by the simulator. C k is the total node capacitance being switched, as determined by the simulator. V is the supply voltage. V is the supply voltage. f is the clock frequency, i.e., the number of vectors applied per unit time f is the clock frequency, i.e., the number of vectors applied per unit time

16. Copyright Agrawal, 2007Lectures 5, 6, 7: Power Analysis16 Gate-Level Power Analysis (Cont.) Monitor dynamic energy events at the input of each gate and obtain internal switching (short circuit) power dissipation: Monitor dynamic energy events at the input of each gate and obtain internal switching (short circuit) power dissipation: P int = Σ Σ E(g,e) F(g,e) gates g events e gates g events e Where Where E(g,e) = energy of event e of gate g, pre-computed short-circuit power from Spice. E(g,e) = energy of event e of gate g, pre-computed short-circuit power from Spice. F(g,e) = occurrence frequency of the event e at gate g, observed by logic simulation. F(g,e) = occurrence frequency of the event e at gate g, observed by logic simulation.

17. Copyright Agrawal, 2007Lectures 5, 6, 7: Power Analysis17 Gate-Level Power Analysis (Cont.) Monitor the static power dissipation state of each gate and obtain the static power dissipation: Monitor the static power dissipation state of each gate and obtain the static power dissipation: P stat = ΣΣ P(g,s) T(g,s)/ T gates g states s gates g states s Where Where P(g,s) = static power dissipation of gate g for state s, obtained from Spice. P(g,s) = static power dissipation of gate g for state s, obtained from Spice. T(g,s) = duration of state s at gate g, obtained from logic simulation. T(g,s) = duration of state s at gate g, obtained from logic simulation. T = number of vectors × vector period. T = number of vectors × vector period.

18. Copyright Agrawal, 2007Lectures 5, 6, 7: Power Analysis18 Gate-Level Power Analysis Sum up all three components of power: Sum up all three components of power: P = P cap + P int + P stat References: References: A. Deng, “Power Analysis for CMOS/BiCMOS Circuits,” Proc. International Workshop Low Power Design, 1994. A. Deng, “Power Analysis for CMOS/BiCMOS Circuits,” Proc. International Workshop Low Power Design, 1994. J. Benkoski, A. C. Deng, C. X. Huang, S. Napper and J. Tuan, “Simulation Algorithms, Power Estimation and Diagnostics in PowerMill,” Proc. PATMOS, 1995. J. Benkoski, A. C. Deng, C. X. Huang, S. Napper and J. Tuan, “Simulation Algorithms, Power Estimation and Diagnostics in PowerMill,” Proc. PATMOS, 1995. C. X. Huang, B. Zhang, A. C. Deng and B. Swirski, “The Design and Implementation of PowerMill,” Proc. International Symp. Low Power Design, 1995, pp. 105-109. C. X. Huang, B. Zhang, A. C. Deng and B. Swirski, “The Design and Implementation of PowerMill,” Proc. International Symp. Low Power Design, 1995, pp. 105-109.

19. Copyright Agrawal, 2007Lectures 5, 6, 7: Power Analysis19 Probabilistic Analysis View signals as a random processes View signals as a random processes Prob{s(t) = 1} = p1 p0 = 1 – p1 C 0→1 transition probability = (1 – p1) p1 Power, P = (1 – p1) p1 CV 2 f ck

20. Copyright Agrawal, 2007Lectures 5, 6, 7: Power Analysis20 Source of Inaccuracy 1/f ck p1 = 0.5 P = 0.5CV 2 f ck p1 = 0.5 P = 0.33CV 2 f ck p1 = 0.5 P = 0.167CV 2 f ck Observe that the formula, Power, P = (1 – p1) p1 C V 2 f ck = 0.25 C V 2 f ck is not correct.

21. Copyright Agrawal, 2007Lectures 5, 6, 7: Power Analysis21 Switching Frequency Number of transitions per unit time: N(t) T=─── t For a continuous signal: N(t) T= lim─── t→∞ t T is defined as transition density.

22. Copyright Agrawal, 2007Lectures 5, 6, 7: Power Analysis22 Static Signal Probabilities Observe signal for interval t 0 + t 1 Observe signal for interval t 0 + t 1 Signal is 1 for duration t 1 Signal is 1 for duration t 1 Signal is 0 for duration t 0 Signal is 0 for duration t 0 Signal probabilities: Signal probabilities: p 1 = t 1/(t 0 + t 1) p 1 = t 1/(t 0 + t 1) p 0 = t 0/(t 0 + t 1) = 1 – p 1 p 0 = t 0/(t 0 + t 1) = 1 – p 1

23. Copyright Agrawal, 2007Lectures 5, 6, 7: Power Analysis23 Static Transition Probabilities Transition probabilities: Transition probabilities: T 01 = p 0 Prob{signal is 1 | signal was 0} = p 0 p1 T 01 = p 0 Prob{signal is 1 | signal was 0} = p 0 p1 T 10 = p 1 Prob{signal is 0 | signal was 1} = p 1 p 0 T 10 = p 1 Prob{signal is 0 | signal was 1} = p 1 p 0 T = T 01 + T 10 = 2 p 0 p 1 = 2 p 1 (1 – p 1) T = T 01 + T 10 = 2 p 0 p 1 = 2 p 1 (1 – p 1)

24. Copyright Agrawal, 2007Lectures 5, 6, 7: Power Analysis24 Static Transition Probability 00.250.50.75 1.0 0.25 0.2 0.1 0.0 p1p1 f = p1(1 – p1)

25. Copyright Agrawal, 2007Lectures 5, 6, 7: Power Analysis25 Inaccuracy in Transition Probability 1/f ck p1 = 0.5 T = 1.0 p1 = 0.5 T = 4/6 p1 = 0.5 T = 1/6 Observe that the formula, T = 2 p1 (1 – p1), is not correct.

26. Copyright Agrawal, 2007Lectures 5, 6, 7: Power Analysis26 Cause for Error and Correction Probability of transition is not independent of the present state of the signal. Probability of transition is not independent of the present state of the signal. Determine probability p 01 of a 0→1 transition. Determine probability p 01 of a 0→1 transition. Recognize p 01 ≠ p 0 × p 1 Recognize p 01 ≠ p 0 × p 1 We obtain p 1 = (1 – p 1) p 01 + p 1 p 11 We obtain p 1 = (1 – p 1) p 01 + p 1 p 11 p 01 p 01 p 1 = ───────── 1 – p 11 + p 01 1 – p 11 + p 01

27. Copyright Agrawal, 2007Lectures 5, 6, 7: Power Analysis27 Correction (Cont.) Since p 11 + p 10 = 1, i.e., given that the signal was previously 1, its present value can be either 1 or 0. Since p 11 + p 10 = 1, i.e., given that the signal was previously 1, its present value can be either 1 or 0. Therefore, Therefore, p 01 p 01 p 1 = ────── p 10 + p 01 p 10 + p 01 This uniquely gives signal probability as a function of transition probabilities.

28. Copyright Agrawal, 2007Lectures 5, 6, 7: Power Analysis28 Transition and Signal Probabilities 1/f ck p01 = p10 = 1.0 p00 = p11 = 0.0 p1 = 0.5 p01 = p10 = 2/3 p00 = p11 = 1/3 p1 = 0.5 p01 = p10 = 1/4 p00 = p11 = 3/4

29. Copyright Agrawal, 2007Lectures 5, 6, 7: Power Analysis29 Probabilities: p0, p1, p00, p01, p10, p11 p 01 + p 00 = 1 p 01 + p 00 = 1 p 11 + p 10 = 1 p 11 + p 10 = 1 p 0 = 1 – p 1 p 0 = 1 – p 1 p 01 p 01 p 1 = ─────── p 10 + p 01 p 10 + p 01

30. Copyright Agrawal, 2007Lectures 5, 6, 7: Power Analysis30 Transition Density T = 2 p 1 (1 – p 1) = p 0 p 01 + p 1 p 10 T = 2 p 1 (1 – p 1) = p 0 p 01 + p 1 p 10 = 2 p 10 p 01 / (p 10 + p 01) = 2 p 1 p 10 = 2 p 0 p 01

31. Copyright Agrawal, 2007Lectures 5, 6, 7: Power Analysis31 Power Calculation Power can be estimated if transition density is known for all signals. Power can be estimated if transition density is known for all signals. Calculation of transition density requires Calculation of transition density requires Signal probabilities Signal probabilities Transition densities for primary inputs; computed from vector statistics Transition densities for primary inputs; computed from vector statistics

32. Copyright Agrawal, 2007Lectures 5, 6, 7: Power Analysis32 Signal Probabilities x1 x2 x1 x2 x1 x2 x1 + x2 – x1x2 x1 1 - x1

33. Copyright Agrawal, 2007Lectures 5, 6, 7: Power Analysis33 Signal Probabilities x1 x2 x3 x1 x2 y = 1 - (1 - x1x2) x3 = 1 - x3 + x1x2x3 = 0.625 X1X2X3Y00010010010101101001101011011111X1X2X3Y00010010010101101001101011011111 0.5 0.25 0.625 Ref: K. P. Parker and E. J. McCluskey, “Probabilistic Treatment of General Combinational Networks,” IEEE Trans. on Computers, vol. C-24, no. 6, pp. 668- 670, June 1975.

34. Copyright Agrawal, 2007Lectures 5, 6, 7: Power Analysis34 Correlated Signal Probabilities x1 x2 x1 x2 y = 1 - (1 - x1x2) x2 = 1 – x2 + x1x2x2 = 1 – x2 + x1x2 = 0.75 (correct value) X1X2Y001010101111X1X2Y001010101111 0.5 0.250.625?

35. Copyright Agrawal, 2007Lectures 5, 6, 7: Power Analysis35 Correlated Signal Probabilities x1 x2 x1 + x2 – x1x2 y = (x1 + x2 – x1x2) x2 = x1x2 + x2x2 – x1x2x2 = x1x2 + x2 – x1x2 = x2 = 0.5 (correct value) X1X2Y000011100111X1X2Y000011100111 0.5 0.75 0.375?

36. Copyright Agrawal, 2007Lectures 5, 6, 7: Power Analysis36 Observation Numerical computation of signal probabilities is accurate for fanout-free circuits. Numerical computation of signal probabilities is accurate for fanout-free circuits.

37. Copyright Agrawal, 2007Lectures 5, 6, 7: Power Analysis37 Remedies Use Shannon’s expansion theorem to compute signal probabilities. Use Shannon’s expansion theorem to compute signal probabilities. Use Boolean difference formula to compute transition densities. Use Boolean difference formula to compute transition densities.

38. Copyright Agrawal, 2007Lectures 5, 6, 7: Power Analysis38 Shannon’s Expansion Theorem C. E. Shannon, “A Symbolic Analysis of Relay and Switching Circuits,” Trans. AIEE, vol. 57, pp. 713-723, 1938. C. E. Shannon, “A Symbolic Analysis of Relay and Switching Circuits,” Trans. AIEE, vol. 57, pp. 713-723, 1938. Consider: Consider: Boolean variables, X1, X2,..., Xn Boolean variables, X1, X2,..., Xn Boolean function, F(X1, X2,..., Xn) Boolean function, F(X1, X2,..., Xn) Then F = Xi F(Xi=1) + Xi’ F(Xi=0) Then F = Xi F(Xi=1) + Xi’ F(Xi=0) Where Where Xi’ is complement of X1 Xi’ is complement of X1 Cofactors, F(Xi=j) = F(X1, X2,.., Xi=j,.., Xn), j = 0 or 1 Cofactors, F(Xi=j) = F(X1, X2,.., Xi=j,.., Xn), j = 0 or 1

39. Copyright Agrawal, 2007Lectures 5, 6, 7: Power Analysis39 Expansion About Two Inputs F = XiXj F(Xi=1, Xj=1) + XiXj’ F(Xi=1, Xj=0) F = XiXj F(Xi=1, Xj=1) + XiXj’ F(Xi=1, Xj=0) + Xi’Xj F(Xi=0, Xj=1) + Xi’Xj’ F(Xi=0, Xj=0) In general, a Boolean function can be expanded about any number of input variables. In general, a Boolean function can be expanded about any number of input variables. Expansion about k variables will have 2 k terms. Expansion about k variables will have 2 k terms.

40. Copyright Agrawal, 2007Lectures 5, 6, 7: Power Analysis40 Correlated Signal Probabilities X1 X2 X1 X2 X1X2Y001010101111X1X2Y001010101111 Y = X1 X2 + X2’ Shannon expansion about the reconverging input, X2: Y = X2 Y(X2 = 1) + X2’ Y(X2 = 0) = X2 (X1) + X2’ (1)

41. Copyright Agrawal, 2007Lectures 5, 6, 7: Power Analysis41 Correlated Signals When the output function is expanded about all reconverging input variables, When the output function is expanded about all reconverging input variables, All cofactors correspond to fanout-free circuits. All cofactors correspond to fanout-free circuits. Signal probabilities for cofactor outputs can be calculated without error. Signal probabilities for cofactor outputs can be calculated without error. A weighted sum of cofactor probabilities gives the correct probability of the output. A weighted sum of cofactor probabilities gives the correct probability of the output. For two reconverging inputs: For two reconverging inputs: f = xixj f(Xi=1, Xj=1) + xi(1-xj) f(Xi=1, Xj=0) + (1-xi)xj f(Xi=0, Xj=1) + (1-xi)(1-xj) f(Xi=0, Xj=0)

42. Copyright Agrawal, 2007Lectures 5, 6, 7: Power Analysis42 Correlated Signal Probabilities X1 X2 X1 X2 X1X2Y001010101111X1X2Y001010101111 Y = X1 X2 + X2’ Shannon expansion about the reconverging input, X2: Y = X2 Y(X2=1) + X2’ Y(X2=0) = X2 (X1) + X2’ (1) y = x2 (0.5) + (1-x2) (1) = 0.5 (0.5) + (1-0.5) (1) = 0.75

43. Copyright Agrawal, 2007Lectures 5, 6, 7: Power Analysis43 Example Point of reconv. Supergate 0.5 0.25 1010 0.5 0.0 1.0 0.5 1.0 Signal probability for supergate output = 0.5 Prob{rec. signal = 1} + 1.0 Prob{rec. signal = 0} = 0.5 × 0.5 + 1.0 × 0.5 = 0.75 0.375 Reconv. signal S. C. Seth and V. D. Agrawal, “A New Model for Computation of Probabilistic Testability in Combinational Circuits,” Integration, the VLSI Journal, vol. 7, no. 1, pp. 49-75, April 1989.

44. Copyright Agrawal, 2007Lectures 5, 6, 7: Power Analysis44 Probability Calculation Algorithm Partition circuit into supergates. Partition circuit into supergates. Definition: A supergate is a circuit partition with a single output such that all fanouts that reconverge at the output are contained within the supergate. Definition: A supergate is a circuit partition with a single output such that all fanouts that reconverge at the output are contained within the supergate. Identify reconverging and non-reconverging inputs of each supergate. Identify reconverging and non-reconverging inputs of each supergate. Compute signal probabilities from PI to PO: Compute signal probabilities from PI to PO: For a supergate whose input probabilities are known For a supergate whose input probabilities are known Enumerate reconverging input states Enumerate reconverging input states For each input state do gate by gate probability computation For each input state do gate by gate probability computation Sum up corresponding signal probabilities, weighted by state probabilities Sum up corresponding signal probabilities, weighted by state probabilities

45. Copyright Agrawal, 2007Lectures 5, 6, 7: Power Analysis45 Calculating Transition Density Boolean function 1 n x1, T1. xn, Tn y, T(Y) = ?

46. Copyright Agrawal, 2007Lectures 5, 6, 7: Power Analysis46 Boolean Difference Boolean diff(Y, Xi) = 1 means that a path is sensitized from input Xi to output Y. Boolean diff(Y, Xi) = 1 means that a path is sensitized from input Xi to output Y. Prob(Boolean diff(Y, Xi) = 1) is the probability of transmitting a toggle from Xi to Y. Prob(Boolean diff(Y, Xi) = 1) is the probability of transmitting a toggle from Xi to Y. Probability of Boolean difference is determined from the probabilities of cofactors of Y with respect to Xi. Probability of Boolean difference is determined from the probabilities of cofactors of Y with respect to Xi. ∂ Y Boolean diff(Y, Xi) =── =Y(Xi=1) ⊕ Y(Xi=0) ∂Xi F. F. Sellers, M. Y. Hsiao and L. W. Bearnson, “Analyzing Errors with the Boolean Difference,” IEEE Trans. on Computers, vol. C-17, no. 7, pp. 676-683, July 1968.

47. Copyright Agrawal, 2007Lectures 5, 6, 7: Power Analysis47 Transition Density n T(y) =Σ T(Xi) Prob(Boolean diff(Y, Xi) = 1) i=1 F. Najm, “Transition Density: A New Measure of Activity in Digital Circuits,” IEEE Trans. CAD, vol. 12, pp. 310-323, Feb. 1993.

48. Copyright Agrawal, 2007Lectures 5, 6, 7: Power Analysis48 Power Computation For each primary input, determine signal probability and transition density for given vectors. For each primary input, determine signal probability and transition density for given vectors. For each internal node and primary output Y, find the transition density T(Y), using supergate partitioning and the Boolean difference formula. For each internal node and primary output Y, find the transition density T(Y), using supergate partitioning and the Boolean difference formula. Compute power, Compute power, P =Σ0.5C Y V 2 T(Y) all Y all Y where C Y is the capacitance of node Y and V is supply voltage.

49. Copyright Agrawal, 2007Lectures 5, 6, 7: Power Analysis49 Transition Density and Power X1 X2 X3 0.2, 1 0.3, 2 0.4, 3 0.06, 0.7 0.436, 3.24 Transition density Signal probability Y CiCi CYCY Power = 0.5 V 2 (0.7C i + 3.24C Y )

50. Copyright Agrawal, 2007Lectures 5, 6, 7: Power Analysis50 Prob. Method vs. Logic Sim. Circuit No. of gates Probability method Logic Simulation Error% Av. density CPU s* Av. density CPU s* C4321603.460.523.3963+2.1 C49920211.360.588.57241+29.8 C8803832.781.063.25132-14.5 C13553464.191.396.18408-32.2 C19088802.972.005.01464-40.7 C267011933.503.454.00619-12.5 C354016694.473.774.491082-0.4 C531523073.526.414.791616-26.5 C6288240625.105.6734.1731057-26.5 C755235123.839.855.082713-24.2 * CONVEX c240

51. Copyright Agrawal, 2007Lectures 5, 6, 7: Power Analysis51 Probability Waveform Methods F. Najm, R. Burch, P. Yang and I. Hajj, “CREST – A Current Estimator for CMOS Circuits,” Proc. IEEE Int. Conf. on CAD, Nov. 1988, pp. 204-207. F. Najm, R. Burch, P. Yang and I. Hajj, “CREST – A Current Estimator for CMOS Circuits,” Proc. IEEE Int. Conf. on CAD, Nov. 1988, pp. 204-207. C.-S. Ding, et al., “Gate-Level Power Estimation using Tagged Probabilistic Simulation,” IEEE Trans. on CAD, vol. 17, no. 11, pp. 1099-1107, Nov. 1998. C.-S. Ding, et al., “Gate-Level Power Estimation using Tagged Probabilistic Simulation,” IEEE Trans. on CAD, vol. 17, no. 11, pp. 1099-1107, Nov. 1998. F. Hu and V. D. Agrawal, “Dual-Transition Glitch Filtering in Probabilistic Waveform Power Estimation,” Proc. IEEE Great Lakes Symp. VLSI, Apr. 2005, pp. 357-360. F. Hu and V. D. Agrawal, “Dual-Transition Glitch Filtering in Probabilistic Waveform Power Estimation,” Proc. IEEE Great Lakes Symp. VLSI, Apr. 2005, pp. 357-360. F. Hu and V. D. Agrawal, “ Enhanced Dual-Transition Probabilistic Power Estimation with Selective Supergate Analysis,” Proc. IEEE Int. Conf. Computer Design, Oct. 2005. pp. 366-369. F. Hu and V. D. Agrawal, “ Enhanced Dual-Transition Probabilistic Power Estimation with Selective Supergate Analysis,” Proc. IEEE Int. Conf. Computer Design, Oct. 2005. pp. 366-369.

52. Copyright Agrawal, 2007Lectures 5, 6, 7: Power Analysis52 Problem 1 For equiprobable inputs analyze the 0 → 1 transition probabilities of all gates in the two implementations of a four-input AND gate shown below. Assuming that the gates have zero delays, which implementation will consume less average dynamic power? Chain structure Tree structure ABCDABCD E F G ABCDABCD E F G

53. Copyright Agrawal, 2007Lectures 5, 6, 7: Power Analysis53 Problem 1 Solution Given the primary input probabilities, P(A) = P(B) = P(C) = P(D) = 0.5, signal and transition (0 → 1) probabilities are as follows: Signal name ChainTree Prob(sig.= 1)Prob(0→1)Prob(sig.=1)Prob(0→1) E0.25000.18750.25000.1875 F0.12500.10940.25000.1875 G0.06250.05860.06250.0586 Total transitions/vector 0.35550.4336 The tree implementation consumes 100×(0.4336 – 0.3555)/0.3555 = 22% more average dynamic power. This advantage of the chain structure may be somewhat reduced because of glitches caused by unbalanced path delays.

54. Copyright Agrawal, 2007Lectures 5, 6, 7: Power Analysis54 Problem 2 Assume that the two-input AND gates in Problem 1 each has one unit of delay. Find input vector pairs for each implementation that will consume the peak dynamic power. Which implementation has lower peak dynamic power consumption? Chain structure Tree structure ABCDABCD E F G ABCDABCD E F G

55. Copyright Agrawal, 2007Lectures 5, 6, 7: Power Analysis55 Problem 2 Solution For the chain structure, a vector pair {A B C D} = {1110}, {1011} will produce four gate transitions as shown below. ABCDABCD E F G A=11 B=10 E=10 C=11 F=10 D=01 G=00 Time units 0 1 2 3

56. Copyright Agrawal, 2007Lectures 5, 6, 7: Power Analysis56 Problem 2 Solution (Cont.) The tree structure has balanced delay paths. So it cannot make more than 3 gate transitions. A vector pair {ABCD} = {1111},{1010} will produce three transitions as shown below. ABCDABCD E F G A=11 B=10 E=10 C=11 D=10 F=10 G=10 Time units 0 1 2 3 Therefore, just counting the gate transitions, we find that the chain consumes 100(4 – 3)/3 = 33% higher peak power than the tree.