1. SEU WG, TWEPP 2011 1 SEU mitigation in GBT On behalf of GBT team Circuit design: TMR Full-custom/High Speed Configuration Registers Protocol Some results with heavy ions Ken Wyllie, CERN

2. SEU WG, TWEPP 2011 2 GBT-SERDES (prototype GBTX) 4.8 Gbit/s serial data 60-bit I/O bus 160 MHz Parallel Out Parallel In/ PRBS Control Logic Phase Shifter dIn [29:0] txClock dOut [29:0] rxClock I2C JTAG RST ClkOut[3:0] Serial input DES Clock Generator Clock ref SER Serial out 120 Digital Core 4.8 Gbit/s serial data Full customSynthesised standard cells Loopback Ken Wyllie, CERN

3. SEU WG, TWEPP 2011 3 Triple-voting in standard cell logic Voter clockA resetA clockB resetB clockC resetC outA outB outC Three independent clock trees Three data paths with voters after every register stage Ken Wyllie, CERN

4. SEU WG, TWEPP 2011 4 Full-custom/High Speed, Config Regs PLL VCOs: enlarge transistor sizes & bias with larger currents => reduce sensitivity to transients (& hence induced jitter) Traditional voting => high propagation delays (4.8 GHz not achievable) => Use ‘transistor-voting’ inside custom flip-flops Configuration Registers Use design from GBLD chip (no clock) Voting gates generate a clock pulse to re-latch correct value Reference: O. Cobanoglu, ‘A radiation tolerant 4.8Gb/s serialiser for the GBT’, TWEPP 2009 Ken Wyllie, CERN

5. SEU WG, TWEPP 2011 5 Protocol 120-bit frame @ 40MHz = 4.8 Gbit/s FEC encoder FEC Forward Error Correction: detect & correct errors (Reed-Solomon code) Motivation: error bursts in PIN diode in receiver Ken Wyllie, CERN

6. 6 SEU tests of GBT Test at Louvain-La-Neuve, Belgium Heavy Ion Facility (cyclotron) Ne (no upsets) Ar (some upsets) Ni (many upsets) Corrections to LET necessary: back-side of chip exposed (C4 package), energy loss through Si, LET enhanced SEU WG, TWEPP 2011 Increasing LET Ken Wyllie, CERN

7. SEU WG, TWEPP 2011 7 Hardware Ken Wyllie, CERN

8. SEU WG, TWEPP 2011 8 Firmware& Software

9. SEU WG, TWEPP 2011 9 Results Continuous BERT during irradiation Read back config registers every 2 secs No latch up No configuration upsets No errors in standard-cell logic (loopback test without SERDES) TX-mode LET threshold ~ 15 MeVcm2/mg…… prediction of low upset rate from Federico Some upsets cause large number of errors in a frame….. To be understood RX-mode…. To be tested Ken Wyllie, CERN