1. 03/30/031 ECE 551 - Digital System Design & Synthesis Lecture 9.0 - Design Partitioning for Synthesis Strategies  Partition for design reuse  Keep related combinational logic together  Avoid glue logic, particularly at top level  Register block outputs  Partition by design goal  Partition by compile technique  Keep sharable resources together  Keep UDRs (User-Defined Resources) with logic they drive  Isolate special functions such as pads, clocks, boundary scan at top level  Place large SRAMs and DRAMS at top core level  Size blocks based on available computational resources

2. 03/30/032 References  Most from section 3 of Design Compiler User Guide (DCUG)  Others from project experience

3. 03/30/033 Design Reuse  Partition so that existing designs can be used in your design  To permit future reuse:  Define and document interface thoroughly  Standardized interface  Parameterize the code

4. 03/30/034 Keeping Related Combinational Logic Together  Reasons:  Default DC cannot move logic across hierarchical boundaries  Logic optimization cannot cross block boundaries  Group related combinational logic & destination register together  Improves logic optimization potential  Enables sequential optimization

5. 03/30/035 Avoid Glue Logic  Glue Logic  Small amounts of logic added to correct interface mismatch or add missing functionality  Eliminating glue logic  Improves logic optimization potential  Reduces compile time  At top level, simplifies floor-planning

6. 03/30/036 Register module outputs  If module outputs are not registered:  long, complex inter-module delay paths can exist Example  Simulation speed is slower due to sensitivity lists that contain more than clock & reset Example  Drive strengths on inputs to modules differ

7. 03/30/037 Register module outputs (continued)  Negatives  Registering outputs may add clock periods to system delays for function execution  Registering outputs may severely restrict module boundary locations

8. 03/30/038 Partition by Design Goal  Design Goals  Area minimization  Delay minimization  By partitioning on design goals:  Allows area constraints on logic without timing issues  Allows timing constraints on logic without area issues  Reduces optimization effort

9. 03/30/039 Partition by Compile Technique  Compile Techniques  Forcing Structure (factoring)  Forcing Flattening (2-level logic)  Examples:  XOR-heavy error detection and correction Circuits should be structured  Random logic should be flattened  Therefore, should not be together in module

10. 03/30/0310 Keep Sharable Resources Together  Only resources within the same always can be shared.

11. 03/30/0311 Isolating Special Functions  Includes pads, I/O drivers, clock generation, boundary scan, and asynchronous modules  The external interface should be at the top level and not placed in modules  Special functions that tie to the interface should be at the next hierarchical level down  Asynchronous functions should be separate modules at an appropriate level of the hierarchy  Example: Figure 3-10 DCUG (See next slide)

12. 03/30/0312

13. 03/30/0313 Place large SRAMs, DRAMS & ROMs at top core level  Relates to physical design interaction with synthesis  Large memory structures need to be placed in the floorplan independently of logic  Floorplanning is needed to do accurate timing analysis and control  Example

14. 03/30/0314 Size blocks based on computational resources  Large blocks permit optimization flexibility  Large block may overwhelm workstation in terms of memory, swap space or processing throughput  Large blocks my cause excessive compile times  Thus, need to select workable intermediate size for blocks