1. Chapter 1_0 Registers & Register Transfer

2. Chapter 1- Registers & Register Transfer  Chapter 7 in textbook

3. DEFINITION OF REGISTERS & COUNTERS Registers and counters, are both sequential blocks.  Registers – used for storing & manipulating data (e.g. arithmetic, logical, boolean).  Counters Used for sequence & control operations. Counters are special types of registers.

4. Register Definitions 1. Includes a set of FFs. 1 FF can store 1-bit of data. An n-bit register, which consists of n- number of FF’s, can store n-bits of data. 2. Consists of a set of FFs, together with gates, that implement their transitions.

5. Register Definitions 3. A set of FFs, possibly with added combinational logic, that perform data-processing tasks. FFs hold data. Gates determine the new or transformed data to be transferred into the FFs.

6. Example : 4 bit Register D D D D D0D0 D1D1 D2D2 D3D3 CLK CLEAR Q0Q0 Q1Q1 Q2Q2 Q3Q3 Q0Q0 Q1Q1 Q2Q2 Q3Q3 D0D0 D1D1 D2D2 D3D3 4 BIT REGISTER SYMBOL LOGIC DIAGRAM Clear = Active LOW Clear = 0 = reset register

7. The 4-bit Register with Parallel Load 1. A common CLK input triggers all FFs on the rising edge of each pulse. Data at the four D inputs are transferred into the 4-bit register. 2. The four Q outputs represents the data stored in the register.

8. … 3. Clear input goes into the R inputs of all FFs useful for clearing the register to all 0’s. Clear is used instead of Clear, because a 0 is needed to reset the FFs asynchronously. Clear is maintained at logic 1 during normal clocked operation.

9. … 4. Loading – is the transfer of information into a register. Parallel loading - if all the bits are loaded simultaneously with a common clock pulse.

10. … 5. Clock pulses are applied to all FFs and registers. The clock input is positive edge-triggered. Master clock generator Supplies a continuous train of clock pulses.

11. How to use LOAD as Control Signal? CLK LOAD CLK FF -When Load =1, CLK FF will follow the CLK (Master Clock) input. - When CLK FF has a PGT (+ve going Transtion) new data will be loaded into register CLK input to Flip Flop Q0Q0 Q1Q1 Q2Q2 Q3Q3 D0D0 D1D1 D2D2 D3D3 CLEAR How?

12. … Load as Control Signal If the contents of the register are not to be changed, the clock must be prevented from reaching the circuit’s clock input: a) Use a separate control signal to govern the clock cycles during this duration, implemented with a load control input, “Load” combined with the clock. CLK FF

13. Cinputs = Load + Clock Load = 1, Cinputs = Clock Register clocked normally. New information can be transferred on positive clock edges. Load = 0, Cinputs = 1 Constant input. No positive clock edges. Contents of register remain unchanged.

14. … Load as Control Signal b) Load must be constant at the correct value, 0 or 1, throughout the interval when Clock = 1. c) “Clock Gating” = turning on and off the clock at CLK FF inputs. d) “Clock skew” = happens when clock signals arrive at the FFs or registers at different times. PROBLEM !

15. “Clock skew” How can clock skew happen? When gates are inserted in the clock pulse, thus producing different propagation delays between Clock and the inputs of FFs having or not having clock gating. Therefore in a truly synchronous system, where all clock pulses MUST arrive simultaneously. Avoid using clock gating. Clock skew must be as close to zero as possible, through control of delays.

16. Registers with Load- Controlled Feedback

18. Load acts as the control input. a) Load is directed through gates instead of through clock gating on the CLK FF inputs.  When Load = 1,  Data on the 4-inputs is transferred into the register, at the next positive clock edge.  When Load = 0,  The data inputs are blocked.  D inputs of FFs connected to the respective FF outputs.  Output is left unchanged.

19. … Load D0D0 Feedback Input x Load When Load = 1, Data on the 4-inputs is transferred into the register, at the next positive clock edge. When Load = 0, The data inputs are blocked. D inputs of FFs connected to the respective FF outputs. Output is left unchanged. D1D1

20. … b) Clock pulses are applied continuously to the CLK FF inputs. c) Load determines whether the next clock pulse will accept new information or leave the information in the register unchanged. d) Transfer of information from inputs to register is still done simultaneously for all 4- bits during a single positive pulse transition. e) This method of transfer is more preferrable; avoids clock skew and the potential for circuit malfunction.

21. Register Transfer Language (RTL)

22. HIGH LEVEL LANGUAGE Example : C+, VB, JAVA ASSEMBLY LANGUAGE Example : uP and uC OPCODE MICROCODE Mircocode (Micro-operations): Operations executed on data stored in registers, performed in one clock cycle Register Transfer Language (RTL): Symbolic notation used to describe micro-operations Register Transfer Language (RTL)

23. RTL Is an algebraic notation used to define machine level operations It is not executed by a computer It is used to explain how the computer works. Example: In 68000 assembly language instruction ADD#3, D2 is define in RTL as [D2] [D2] + 3 Register Transfer Language (RTL)

24. Types of Registers  AR (Address Registers)  DR (Data Registers)  PC (Program Counters)  IR (Instruction Registers)  Rn (n indicates the Register number, eg R2)

25. Block Diagram of Registers R PC(H) Register 16 bit Register 7 8 bit Register 6543210 Bit 7Bit 0 15141312111098 76543210 Bit 16 Bit 0 PC(L) 8 bit = 1 byte H = High order byte L = Low order byte PC(H) = PC(15:8) PC(L) = PC(7:0)

26. BASIC SYMBOLS  R followed by a number is referring to a register: R2 = second register/register no 2 R2

27. BASIC SYMBOLS  M refers to Memory with addresses in square braces: Direct Addressing : M[10] = contents of memory address 10 In this example, M[10] refers to 10111011 10000000 10111011 11111111 9 10 11 AddressContent MEMORY

28. BASIC SYMBOLS  M refers to Memory with addresses in square braces In-direct Addressing : M[R3] = content of the memory address in R3 10000000 10111011 11111111 15 16 17 AddressContent MEMORY 10000000 00000110 00001111 1 2 3 AddressContent REGISTER 00001111 = 15 Ans : M[R3] refers to 10000000

29. BASIC SYMBOLS  Arrow pointing to the right shows transfer of data : R4R3 = Stores the value of R3 to R4 * The word transfer is misleading, since it implies that data is moved from one location to another. In fact, the data is copied from one location to another since it also still resides in register R3

30. BASIC SYMBOLS  A comma represents simultaneous transfer: R1 R2, R6 R7 = Stores R2 into R1 and at the same time stores R7 into R6.

31. BASIC SYMBOLS  Parenthesis indicates part of the register. R8(1) = the second least significant bit of R8 R8 76534210 10111000 Bit Position Content MSB LSB LSB : Least Significant Bit MSB : Most Significant Bit

32. BASIC SYMBOLS  Parenthesis indicates part of the register. R3(7:0) = the least significant byte of R3 Note : 1 byte = 8 bit R3 76534210 10111000 14..9158 1 0..1

33. MATHEMATICAL AND LOGICAL SYMBOLS  Addition is indicated by the + sign: R1R2+R3 Add R2 and R3, stores in R1 R2R4+R1 Add R4 and R1, stores in R2 Example 1 : Example 2 :

34. MATHEMATICAL AND LOGICAL SYMBOLS  Subtraction is handled not with the minus sign but with complementing.  1’s complement :  2’s complement : R5R3+R4 R5R3+R4+1 R3 minus R4 in 1’s complement R3 minus R4 in 2’s complement

35. MATHEMATICAL AND LOGICAL SYMBOLS  QUIZ RTL : R8 R1+R2+1 What is the value of R8 if R1 = 01010010 and R2 = 00100011.

36. Remember the 2’s complement rules? Rules for subtracting A from B - Form the 2’s compliment of A - Add Compliment of A to B - If a Carry results Thendiscard carry Result is positive : no further action required else (meaning NO Carry) Result is negative : form the 2’s comp of the result position a “-” sign.

37. Quiz Answer RTL : R8 R1+R2+1 R1 = 01010010 R2 = 00100011 2’s Comp of R2 = 11011101 Add 01010010 (R1) and 11011101 (2’s comp R2) Toggle the number Add 1 01010010 11011101 + 100101111 Carry bit Refer to rules: Discard carry Result is positive, no further action required

38. Quiz Answer….cont Double check : R1 = 82 R2 = 35 R1 minus R2 = 68 – 35 = 47 47 in binary = 00101111 Answer keep in R8 = 00101111

39. Summary SymbolDescriptionExample Square brackets Specifies an address for memory M[R2] LettersDenotes a registerAR, IR, PC, R2 ParenthesesDenotes part of a register R2(1), R2(7:0), PC(L) ArrowDenotes Transfer of data R1 R2 CommaSeparates simultaneous transfers R1 R2, R3 R2