1. CTL – 1450.6.2 Redundancy sub-team update 09/11/2009 Team: Slimane,Saman,Gary,Karen,Srinivas,Rajat

2. Scope To model information for memory repair –Model Memory Redundancy Type of redundancy (column, row etc.) Reparability (block / bank association) –Model Memory Repair mechanism Describe pin functions for repair Describe repair data

3. CTL Redundancy - model MemoryRepair { // one block summarizing all repair info of the corresponding memory RedundancyElement { // 1 RedundancyElement block per spare unit // Defines reparability with the redundancy element Type ; Width // width of the resource, defaulted to 1 AddressMap // defines the possible starting addresses of that element p, and q can take any value provided that // starting_add belong to Column/Row AddressRange RowAddressRange [R..0] // required if the spare unit has restriction on the rows to replace - refers to the logical address ColumnAddressRange [C..0] // required if the spare unit has restriction on columns to replace DataRange [D..0] // required if the spare unit has restriction on the data I/O to replace // Defines memory repair data EnableConnectivity { { = ;} // Defines enable / disable state of red. Element } DataConnectivity {// Primarily used for column repair – data bit dependency {RepairValue= ; AssociatedSignal= }// Defines a repair value for each data port } AddressConnectivity {// Primarily used for row / IO repair – address bus dependency { RepairSignal= ;}// Defines the memory signal that defines repair value for RepairPort } RedundancyElement {…} … RedundancyElement {…} … }

4. Example 1 : Memory Architecture 8224 words, 14 bits, mux 16

5. Example 1 : Redundancy Description Any spare row in bottom bank can repair any row in the bottom bank Any spare row in the top bank can repair either of the rows (only 2) in the top bank Any group of 8 columns in left array can be repaired Any group of 8 columns in the right array can be repaired

6. Example 1: CTL (1) Signals { “Q”[13..0] Out; “A”[13..0] In;“D”[13..0] In; “CRE1” In; “FBA1” [3..0] In “CRE2” In; “FBA2” [3..0] In “RRE1” In “FRA1”[8..0] In “RRE2” In; “FRA2”[8..0] In; “RRE3” In; “FRA3” In; “RRE4” In; “FRA4” In } Environment “Memory1” { CTL { CRE1 { DataType RepairEnable {ActiveState ForceUp;}} FBA1[3:0] {DataType RepairAddress;} CRE2 { DataType RepairEnable {ActiveState ForceUp;}} FBA2[3:0] { DataType RepairAddress;} RRE1 {DataType RepairEnable {ActiveState ForceUp;}} FRA1[8..0] {DataType RepairAddress;} RRE2 {DataType RepairEnable {ActiveState ForceUp;}} FRA2[8..0] {DataType RepairAddress;} RRE3 {DataType RepairEnable {ActiveState ForceUp;}} FRA3 {DataType RepairAddress;} RRE4 {DataType RepairEnable {ActiveState ForceUp;}} FRA4 {DataType RepairAddress;} }

7. MemoryRepair { RepairResource column1 { Type Column; Width 8 AddressMap 8n // logical address ColumnAddressRange [0..15] RowAddressRange [0.. 513] DataRange [0..6] EnableConnectivity { CRE1 {RepairValue= 1} } AddressConnectivity { FBA1[3:0] {RepairSignal=A[3:0]} } RepairResource column2 { Type Column; Width 8 AddressMap 8n ColumnAddressRange [0..15] RowAddressRange [0.. 513] DataRange [7..14] EnableConnectivity { CRE2 {RepairValue = 1} } AddressConnectivity { FBA2[3:0] {RepairSignal=A[3:0} } RepairResource row1{ Type Row; Width 2 AddressMap n ColumnAddressRange [0..15] RowAddressRange [0.. 511] DataRange [0..6] EnableConnectivity { RRE1 {RepairValue= 1} } AddressConnectivity { FRA1[8:0] {RepairSignal= A[8:0} } RepairResource row2 { Type Row; Width 2 AddressMap n ColumnAddressRange [0..15] RowAddressRange [0.. 511] DataRange [7..14] EnableConnectivity { RRE2 {RepairValue= 1} } AddressConnectivity { FRA2[8:0] {RepairSignal= A[8:0]} } RepairResource row3 { Type Row; Width 2 AddressMap n ColumnAddressRange [0..15] RowAddressRange [512.. 513] DataRange [0..6] EnableConnectivity { RRE3 {RepairValue=1} } AddressConnectivity { FRA3 {RepairSignal = A[0} } RepairResource row4 { Type Row; Width 2 AddressMap n ColumnAddressRange [0..15] RowAddressRange [512.. 513] DataRange [7..14] EnableConnectivity { RRE3 {RepairValue= 1} } AddressConnectivity { FRA4 {RepairSignal= A[0]} } Example 1: CTL (2)

8. Example 2 : Memory redundancy Description Memory with 4 IO redundant units Each IO Unit can replace an IO in a segment of 4 columns All redundant Units are swapped if any of the IOs in any segment is faulty Redundant IOs Q0 Q1 R1R2R4R3Q4Q15

9. Example 2: CTL Signals { “Q”[15..0] Out; “A”[13..0] In;“D”[15..0] In; “EN” In; “FAL”[1..0] In } Environment “Memory2” { CTL { EN { DataType RepairEnable {ActiveState ForceUp;}} FAL[1:0] {DataType RepairAddress;} } MemoryRepair { RepairResource column1 { Type Column Width 4 EnableConnectivity { En {RepairValue=1} } DataConnectivity { FAL[1:0] { RepairValue = “00”; AssociatedElement={D[0],D[4],D[8],D[12]} RepairValue = “01”; AssociatedElement={D[1],D[5],D[9],D[13]} RepairValue = “10”; AssociatedElement={D[2],D[6],D[10],D[14]} RepairValue = “11”; AssociatedElement={D[3],D[7],D[11],D[15]} }

10. Example 3 : Memory description Words : 128 Width : 32 ColMux : 1 A[6:0] D[31:0] Q[31:0] FAT[5:0] FET FAB[5:0] FEB Memory I/f Description Memory has a split architecture which divides the memory into 2 banks (Top and Bottom ). Most significant Q are on the left, least significant are on the right. Each bank always has one redundant row. The row group that is bad causes the rest of the row groups to shift towards the redundant row. Redundancy is activated by blowing the address of the row group. row 0 row 31 row 63 row 32 row 127 row 96 row 64 row 95 Q … Q 3 …. 0 1 Shift direction

11. Example 3 : CTL MemoryRepair { RedundancyElement row1{ Type Row; Width 1 DataRange [0..31] AddressMap n RowAddressRange [0.. 31, 64.. 95] EnableConnectivity { FET {RepairValue = 1} } AddressConnectivity { FAT[5] {RepairSignal = A[6]} FAT[4:0] {RepairSignal = A[4:0]} } RedundancyElement row2 { Type row; Width 1 DataRange [0..31] AddressMap n RowAddressRange [32..63,96.. 127] EnableConnectivity { FEB {RepairValue = 1} } AddressConnectivity { FAT[5] {RepairSignal = A[6]} FAT[4:0] {RepairSignal = A[4:0]} } Signals { “Q”[31..0] Out; “A”[6..0] In;“D”[31..0] In; “FET” In; “FAT”[5..0] In; “FEB” In; “FAB”[5:0] In; } Environment “Memory2” { CTL { FET { DataType RepairEnable {ActiveState ForceUp;}} FAT[5:0] {DataType RepairAddress;} FEB { DataType RepairEnable {ActiveState ForceUp;}} FAB[5:0] {DataType RepairAddress;} }