1. DIGITAL COMPONENTS

2. MULTIPLEXERS A multiplexer is a combinational circuit that receives binary information from one of 2 n input data lines and directs it to a single output line. ◦ A selector chooses a single data input and passes it to the MUX output ◦ It has one output selected at a time.

3. A 2 n to 1 multiplexer has 2 n input data lines and n input selection lines whose bit combinations determine which input data are selected for the output. A 4-to-1-line multiplexer is shown in fig.

4. S1S1 S0S0 F 00I0 01I1 10I2 11I3

5. Each of the four data inputs I0 through I3 is applied to one input of an AND gate.The two selection inputs S1 and S0 are decoded to select a particular AND gate.The output of the AND gate are applied to a single OR gate to provide the single output. The multiplexer is also called a data selector,since it selects one of many data inputs and steers the binary information to the output.

6. Quadruple 2-to-1 Line Multiplexer

7. E (Enable) S (Select) Y (Output) 0XAll 0’s 10A 11B

8. The circuit has four multiplexer,each capable of selecting one of two input lines. Output Y0 can be selected to come from either input A0 or B0.Similarly output Y1 may have the value of A1 or B1 and so on.One input selection line S selects one of the lines in each of the four multiplexers.The enable E must be active for normal operation.

9. SHIFT REGISTER A register capable of shifting its binary information in one or both directions is called a shift register. It consists of a chain of flipflop in cascade,with the output of one flipflop connected to the input of the next flipflop.All flipflop receive common clock pulse that initiate the shift from one stage to the next.

11. Shift registers can also be loaded using parallel input lines Therefore inputs can be parallel or serial Outputs can be parallel or serial

12. Shift Register with parallel load

13. If the register has both shifts and parallel load capabilities, it is referred to as a universal shift register. A clear control to clear the register to 0. A clock input to synchronize the operations. A shift-right control to enable the shift right operation and the serial input and output lines associated with the shift right.

14. A shift-left control to enable the shift left operation and the serial input and output lines associated with the shift left. A parallel-load control to enable a parallel transfer and the n input lines associated with the parallel transfer. n parallel output lines A control state that leaves the information in the register unchanged in the presence of the clock.

15. S1, S0 -> 0, 0 ;No change S1, S0 -> 0, 1 ; Shift right, The serial input for shift-right is transferred to the A3. S1, S0 -> 1, 0 ; Shift left, The serial input for shift-left is transferred to the A0. S1, S0 -> 1, 1 ;Parallel load

16. BINARY COUNTER A register that goes through a prescribed sequence of states upon the application of input pulses is called a counter. The input pulses may be clock pulses or they may originated from some external source and may occur at a fixed interval of time or at random.

17. A counter that follows the binary number sequence is called a binary counter. An n-bit binary counter consists of n flip- flops and can count in binary from 0 to 2^n -1. Synchronous binary counters,clock pulses are applied to the inputs of all flip- flops.

19. If the count enable is 0,all J and K inputs are maintained at 0 and the output of the counter does not change. The first stage A0 is complemented when the counter is enabled and the clock goes through a positive transition. A flip-flop in any other position is complemented when all the bits in the lower significant positions are equal to 1.

20. Binary Counter with Parallel Load

21. Load=0 and count=0 ;unchanged Load =0 and count=1 ;increment count by 1. Load=1 and count= x;Load input I0 through I3.