1. Microprocessor Fundamentals Week 2 Mount Druitt College of TAFE Dept. Electrical Engineering 2008

2. © Mike Stacey 2007 Stored Program Concept (p1 & last week) Program stored in memory so that it can be changed Previously, program was part of the control unit and required “rewiring” in order to change it Who thought of this idea? Machine Language  μP recognises certain bit patterns representing instructions  The bit patterns are called machine language

3. © Mike Stacey 2007 Op-codes and Operands (p1) Machine language consists of 2 parts:  Op-code: first part of the instruction tells the μP what kind of basic operation will be carried out. Example: STORE, SHIFT, JUMP, ADD  Operand: The following bits provide information such as the data that is to be operated on and the place it will be stored MOV AX, BX  Moves (copies) data from register BX to AX

4. © Mike Stacey 2007 Machine Cycle (p1) 1.Fetch Instruction from memory 2.Decode Decode instruction – work out what to do with it by interpreting the op-code and operand fields 3.Execute Execute it – run it

5. © Mike Stacey 2007 Data, Addresses and Registers in the Z80 The Z80 uP uses 8 bit bytes for data and accesses this data using 16 bit addresses.  How many separate address locations are there? Registers inside the uP are used for storage of numbers  There are 8 bit registers for storing numbers the program is operating on and also 16 bit registers for storing addresses of data See page 1 for list of registers

6. © Mike Stacey 2007 Machine Cycle, how? (no ref) In general:  Within the control unit there are 2 special purpose registers: the program counter (instruction pointer IP) and the instruction register (IR).  Program counter: contains the address of the next instruction – keeps track of what step the execution is at  Instruction register holds the current instruction being executed

7. © Mike Stacey 2007 Machine cycle, how? (no ref) Control unit repeats the machine cycle, fetch, decode, execute Fetch: control unit knows where the next instruction is because its address is in the program counter. Control unit retrieves instruction from memory – places into instruction register, then increments the program counter…why?

8. © Mike Stacey 2007 Machine cycle, how? (no ref) Decode: control unit now decodes instruction which involves breaking the instruction into pieces. Execute: control unit then executes instruction by activating the appropriate circuitry for the task at hand. Example: the instruction might be an ADD – it would then invoke circuitry inside the ALU. Next step?

9. © Mike Stacey 2007 μP Components (P1,2,3…) Registers  Temporary storage of data or program General purpose: storage of data for ALU input and output. Control unit transfers data from memory to these registers, informs ALU where the data is and activates circuitry inside ALU Special purpose: such as program counters and instruction register  Registers are the fastest type of memory

10. © Mike Stacey 2007 Many steps for simple instructions (no ref) Instruction: Add 2 values 1.Get one of the values from memory and store in a register 2.Get the other value from memory and store in another register 3.Activate addition circuits in ALU with registers in steps 1 and 2 as inputs and another register to hold the output 4.Store result in memory (transfer from output register to memory) 5.Stop

11. © Mike Stacey 2007 Memory Hierarchy (no refs) Disk Main Memory (RAM) Cache µP Registers Data immediately applicable to operation at hand Data required in near future Data required in VERY near future Data not required in near future

12. © Mike Stacey 2007 8086 µP (p3-5) Contains 2 primary register groups 1.Bus Interface Unit (BIU): calculates addresses and handles all transfers of data and addresses for the Execution Unit. All information to/from the address and data busses takes place via the BIU. 2.Execution Unit (EU): Execution Unit receives program instruction codes and data from BIU (via instruction queue), decodes and executes these instructions and stores results in the general registers.

13. © Mike Stacey 2007 BIU (p3-4) Fetches instructions from memory and places into FIFO queue registers from where the EU retrieves them Can fetch up to 6 ahead of time Can be fetching instructions at the same time as EU is executing them – called pipelining Each program contains addresses for code, data, extra and stack memory areas BIU contains segment registers for memory addressing  Code segment (CS): program code  Data segment (DS): program data  Extra segment (ES): string operations  Stack segment (SS): stack operations (a stack is a type of data structure) Also contains the instruction pointer (IP) or program counter (PC) register

14. © Mike Stacey 2007 8086 μP (p3)

15. © Mike Stacey 2007 Example MOV, AX, [2456]: moves data from address 2456 into register AX. However 2456 is not the physical address of the data.  BIU grabs the instruction and calculates the physical address of the data that is to be moved  Supplies the physical address of the data to the EU so the EU knows where to get the data from (in RAM) Look at the diagram on page 3. The adder and the segment registers are used for the calculation of the physical address.

16. © Mike Stacey 2007 Segment Registers and Addressing Memory (p3-4) – Memory Segmentation Code, Data, Stack, Extra segments Each segment contains different types of data or instructions 8086 has a 20 bit internal address bus so it can address 2 20 (1MB) locations (each containing 1 byte) The CS, DS, SS and ES registers contain the base addresses of each 64KB segment If DS register contains 2456 then 2456 is shifted left by 4 bits to give 24560 – this is the start (base) address for the data segment

17. © Mike Stacey 2007 Addressing Memory (p3 & p11) Code Stack Data Extra 64kB Base address: 490B0 Physical address: 4B506 Effective add.: 02456 CS SS DS:490B ES MEMORY SEGMENT REGISTERS Memory divided into logical areas needed for program addressing Each segment holds 64kB Base address: XXXX0

18. © Mike Stacey 2007 Effective address and physical address (p4) Effective address: offset from base address Base address: start address for segment Physical address: actual physical address in memory Data segment address: 490B Data segment base address: 490B0 Effective address (EA): 02456 Physical address: 4B506 See example p4. Also see example instruction: MOV,AX,[2456]

19. © Mike Stacey 2007 example.com Identify the registers, code segment base address and effective address of each instruction byte.

20. © Mike Stacey 2007 Instruction Pointer Register (p4) The Instruction Pointer register holds the 16-bit address of the next instruction byte, relative to the base address contained in the Code Segment register CS. The logical address is written as CS:IP. For example if CS = 034F and IP = 001C then the physical address of the next instruction to be fetched from memory is 034F0 + 001C = 0350C so the logical address would be written as 034F:001C

21. © Mike Stacey 2007 The Execution Unit (p4-5) Contains:  ALU  Control Unit (CU)  Flag Register: see p5 table, status and control flags  General Purpose Registers AX, BX, CX, DX: each can be 1 x 16 bit or 2 x 8 bit regs. Example: AL and AH – low and high bytes for AX Stack Pointer Registers BP and SP: contain offset addresses which are used in conjunction with SS register to access data on the stack, see example p5.  Index Registers

22. © Mike Stacey 2007 Review Questions & Prac. Do questions 1 – 7. Complete debug pracs 1 & 2 then begin debug prac 3. Note:  Format your text file prac results carefully according to guidelines provided by the teacher  Organise your work logically into weekly directories on your flash disk  Back up your work at home onto hard disk or another flash disk! This is your own responsibility. If the work is lost, it hasn’t been done.