1. ECE 3450 M. A. Jupina, VU, 2016 Capacitance Sensor Project Goal: Creation of a digital capacitance sensor circuit where a variation in capacitance changes the frequency or period of oscillation of a timer circuit. A FPGA circuit then measures this change in the time period and displays an integer value between 0 to 99 (base 10) to indicate the amount of capacitance. A capacitance value of C min would be indicated by a value of 0 and a value of C max would be indicated by a value of 99. The current maximum value will be stored by the sensor circuit and displayed on the seven-segment LED displays on the DE2 board.

2. Capacitance Sensor Project 555 Timer variable frequency or period OUTPUT 0 - 99 7-segment displays d H a b Sports Applications Tank Application ECE 3450 M. A. Jupina, VU, 2016

3. Application of Your Capacitance Sensor Assume that you are designing an impact sensor for a boxing glove where you want to capture only the maximum impact of the glove on a boxing bag during a training session. For a range of possible impacts, assume that no impact on the capacitance sensor is a value of C min, whereas the maximum possible impact on the capacitance sensor by a boxer such as Mike Tyson would be a value of C max. The display on the glove would indicate a value of 0 for no impact and a value of 99 if Mike Tyson hit a boxing bag with the glove. A reset button will also be available to clear the sensor so that the maximum impact value can again be captured. ECE 3450 M. A. Jupina, VU, 2016

4. Specifications of Your Capacitance Sensor Assume that the capacitance of the sensor varies as a linear function of the impact applied to the boxing glove. The maximum capacitance that can be measured by the sensor is C max = 4 C min Therefore, the range of capacitance that is to be measured is  C = C max - C min = 3 C min When C=C min, the period of the timer circuit will be T min, whereas when C=C max the period of the timer circuit is T max since the period of the timer circuit increases as the RC time constant time increases. The timer circuit will be a 555 timer. ECE 3450 M. A. Jupina, VU, 2016

5. Implementation of Your Capacitance Sensor An 8-bit counter in the Timer_Count block will be used to measure the period of oscillation of the timer circuit. The clock frequency used by the 8-bit counter can be one of the following frequencies: 1 KHz, 10 KHz, or 100 KHz. Use the following C min values depending on your lab station #: o C min = 0.001  F, for lab stations 1, 4, 7, 10, 13, & 16 o C min = 0.01  F, for lab stations 2, 5, 8, 11, 14, & 17 o C min = 0.1  F, for lab stations 3, 6, 9, 12, 15, & 18 A subtraction circuit will be used to null the value of the counter when T=T min by offsetting the output value such that it equals 0 when T=T min. Thereby, a value of 99 at the output represents the time period  T = T max – T min (Note:  T is directly proportional to  C). ECE 3450 M. A. Jupina, VU, 2016

6. Block Diagram of the Capacitance Sensor CLK_DIV - Seven_Seg_Display 50 MHz Oscillator f, T f/2, 2T TIMER_COUNT OFFSET 0 to 99 1KHz 10KHz or 100KHz When C = C min, Output = 0 When C = C max, Output = 99 Reset ECE 3450 M. A. Jupina, VU, 2016

7. Quartus Block Diagram File to Verify Functionality ECE 3450 M. A. Jupina, VU, 2016

8. Quartus II Simulation ? ?? On this time scale, the details of this signal are not seen since its period is too small. Counter in Timer_Count block is counting Output in Timer_Count block is again increasing since count_final > count_temp count_temp < count_final so count_temp value is not captured since only the max value is captured ECE 3450 M. A. Jupina, VU, 2016

9. Prelab Assignment Pre-Lab i.For your given C min and C max values, determine the possible values of  T (=R  C) given that the R values will be either in the K  10’s K  or low 100’s K  range (possible resistor values are 1K, 2.2K, 3.3K, 4.7K, 10K, 22K, 33K, 47K, and 100K and can be combined in series or parallel configurations to achieve specific values). Given the possible  T values and the fact that an 8-bit counter will be used, what clock periods are possible? ii.For your possible  T values, design a 555 timer circuit to meet the specifications described in slides 4 and 5. Select one of these circuits as your final design. iii.Finish the Timer_Count VHDL code shown on the next page such that a.If the reset is LOW, clear all signal inputs (lines 24-26). b.On each rising edge of the clock signal, if the timer_2x input is HIGH, then increment the count value by 1 and temporarily store the count (count_temp), otherwise clear the count value (lines 28- 33). c.Store only the maximum count value (count_final) (lines 35-39). d.The output of count value (count_out) is the final count value (line 43). ECE 3450 M. A. Jupina, VU, 2016

10. Unfinished Timer_Count VHDL Code ECE 3450 M. A. Jupina, VU, 2016

11. Additional Guidelines for the Timer Circuit Design  T = R *  C where the time period  T is also equal to 99 clock periods (possible clock periods, T clk, are 10  s, 100  s, or 1000  s). Depending on the  C value (3*C min ) given to you and the R value that you choose will determine which T clk values are possible. 2. Once possible  T values are known, possible T min and T max values are thereby known. Given a certain T min or T max value, you should be able to design a 555 timer circuit that oscillates with a period of T min or T max depending on the C value in the circuit. The R values in these timer circuits will be approximately the same value (or at least the same-order-of-magnitude) as the R value that was first determined in guideline 1. 3. For the 555 timer circuit, use the formulas for the period of oscillation (T) from the topic 5 class lecture ppt file. ECE 3450 M. A. Jupina, VU, 2016

12. Lab Procedure Work to be preformed in the Lab: 1)Compile and simulate a sensor circuit like the one shown in slide 7 (call it capsensor1.bdf). Your simulation should be similar to the one depicted in slide 8. 2)Start a new project. Add a timer input signal, a Reset signal (KEY3), offset value (SW7-SW0), a CLOCK signal (derived from the 50 MHz signal and the clk_div block), a block to drive the seven segment LED output displays, and pin assignments to the previous design (call it capsensor2.bdf now) and compile it (no need to simulate this design since you verified its functionality in capsensor1 project). After successful compilation, download the design to the DE2 board and then verify the operation of your capacitance sensor over a range of capacitance values. ECE 3450 M. A. Jupina, VU, 2016

13. Simple ADDER VHDL Code ECE 3450 M. A. Jupina, VU, 2016

14. Figure 6.25. A BCD-to-7-segment display code converter. ECE 3450 M. A. Jupina, VU, 2016 ce 1 0 1 1 1 1 1 w 0 a 1 b 01 1 1 1 0 1 1 0 1 0 0 w 1 0 1 1 0 0 w 2 0 0 0 0 1 w 3 0 0 0 0 0 c 1 0 1 0 0 1 1 0 1 1 1 0 0 0 0 1 1001 1 1 1 1 0 1 1 0 11 1 1 1 1 1 0 1 1 1 d 0 1 0 0 1 0 e 1 0 1 1 1 0 1 0 0 1 0 0 0 1 f 1 0 0 1 1 1 g 1 0 1 1 1 1 1 1 0 1 (c) Truth table (a) Code converter w 0 a w 1 b c d w 2 w 3 e f g a g bf d (b) 7-segment display

15. Figure 6.47. Code that represents a BCD-to-7-segment decoder. ECE 3450 M. A. Jupina, VU, 2016 LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY seg7 IS PORT (bcd : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; leds: OUT STD_LOGIC_VECTOR(1 TO 7) ) ; END seg7 ; ARCHITECTURE Behavior OF seg7 IS BEGIN PROCESS ( bcd ) BEGIN CASE bcd IS --abcdefg WHEN "0000" => leds <= "1111110" ; WHEN "0001" => leds <= "0110000" ; WHEN "0010" => leds <= "1101101" ; WHEN "0011" => leds <= "1111001" ; WHEN "0100" => leds <= "0110011" ; WHEN "0101" => leds <= "1011011" ; WHEN "0110" => leds <= "1011111" ; WHEN "0111" => leds <= "1110000" ; WHEN "1000" => leds <= "1111111" ; WHEN "1001" => leds <= "1110011" ; WHEN OTHERS => leds <= " ------- " ; END CASE ; END PROCESS ; END Behavior ;

16. ECE 3450 M. A. Jupina, VU, 2016 Hexadecimal to 7-Segment Decoder ETC. Input Outputs

17. Unfinished Seven_Seg_ Display VHDL Code ECE 3450 M. A. Jupina, VU, 2016

18. Clock Divider for DE2 The clock_50MHz input is connected to pin number N2.

19. DE2_pin_assignments.csv File ECE 3450 M. A. Jupina, VU, 2016

20. Pin Assignments for DE2 Board 1.Reset switch ( KEY[3] ) is PIN_N25 2.50 MHz clock ( CLOCK_50 ) is PIN_N2 3.Input ( GPIO_0[1] ) is PIN_J22 (Pin 2 on JP1) 4.Common Ground is Pin 12 on JP1 5.Seven Segment Displays (HEX0[0] to HEX0[6] and HEX1[0] to HEX1[6] ) are pins … ECE 3450 M. A. Jupina, VU, 2013

22. Clock Inputs ECE 3450 M. A. Jupina, VU, 2013

24. Header Pin Assignments ECE 3450 M. A. Jupina, VU, 2013

25. Header Pin Assignments ECE 3450 M. A. Jupina, VU, 2013

27. Seven Segment Displays ECE 3450 M. A. Jupina, VU, 2016

29. Lab Measurement Details 1)Measure the values of the capacitors that you are using for testing on a capacitance meter. 2)On the scope, also measure the period of oscillation (T) of the output signal from the timer circuit under the different capacitance values. 3)Make a table showing the C value, T value, and the output value shown on the display. Demonstrate through calculations that the C, T, and the output values are correct. If slight differences exist, what are the possible sources of error? 4)Demonstrate that if the capacitance value is reduced, the output display does not change (i.e., only the max value is displayed). After pressing the reset button, does the display now show a value consistent with the current capacitance value? 5)Finally, verify the functionality of your design by capturing the same signals within your design as shown on slide 8 using the Signal Tap II Logic Analyzer. ECE 3450 M. A. Jupina, VU, 2016

30. An Example of Settings for Signal Tap II Logic Analyzer @1: EP2C35 (0x020B 40DD)

31. ECE 3450 M. A. Jupina, VU, 2016 Example of Signals Displayed in Signal Tap II @1: EP2C35 (0x020B 40DD)

32. An Example Design Illustrating the Mapping of Multi-Bit Connections ECE 3450 M. A. Jupina, VU, 2016