1. Efuse block Description and simulation

2. Symbol 2 16 out_bus 6 address NR1 Sense Burn_CK Burn_RN sub gndd subCon T3NW vddp vddd FEI4_A_EFUSE Burn_srout EFUSE_errorflag WE 48 out_still NR2 16 in_bus

3. I/O list 3 Pin nameDescriptionComment Address INPUT - 6-bit address busProvided by CMD block in_bus INPUT - 16-bit data busFrom CMD block out_bus OUTPUT - 16-bit data busTo EOCHL block out_still OUTPUT – 48 bit data bus To end of column Shift Register Select (40b), voltage ref trim (4b) and current ref trim (4b) NR1 INPUT – General ResetActive low – reset when NO (NR1 AND NR2) NR2 INPUT – General ResetActive low – reset when NO (NR1 AND NR2) Burn_RN INPUT - EFUSE reset Active low Reset the sense state machine and the EFUSE internal memory. Burn_CK INPUT - Independent EFUSE readout shift register clock Rising edge data sampling Falling edge data shift Clock to independently output the EFUSE values. From pad Burn_srout OUTPUT – Shift register output Shift register output. Flag the end of the programming sequence or read out programmed values – To dig buffered pad Sense INPUT – Start the sense circuitry – Rising edge Start the sense circuitry. From control block EFUSE_errorflag OUTPUT – active high Flag an error in latches To error block WE INPUT - Write enable Validate a write in the latch from the data bus From CMD block Vddp Program VddTyp 3.3V, Min 3V, 15mA flowing during prog. Vddd Digital VddTyp. 1.4V T3Con Triple Well contactTo be tied to dedicated vdd Sub Substrate- Gndd Digital Ground15mA flowing during programming SubCon Substrate contact-

4. Block Scheme 4 Data bus out Address bus EFUSE out bus 64 bits EFUSE in bus 64 bits Burn_CK Burn_RN Burn_srout Error_flag Sense EFUSE CORE COM MODULE Data bus in Still Data bus

5. Com Block Scheme 5 Data bus out Address bus EFUSE out bus, 64 bits EFUSE in bus, 64 bits Error_flag Data bus in Still Data bus WORD address 32 WORD address 33 WORD address 34 WORD address 35 Address decoder WE Re-sense

6. Layout 6

7. 7 How to write Writing sequence : –3.3V is down –chip is reseted and EFUSE is reseted –Data are sent to the EFUSE register –3.3V is turned on –Burn_CK starts until the one that is propagating reach the register output  Bit are written one after another to avoid excessive current in the chip (10-13mA per bit)

8. Burn Simulation 8 In that simulation, the latches are loaded with word 1010101010101010 at address 32, all the other latches are kept at 0. The burn process is then started and the current flowing out of Vddp is sensed.

9. 9 How to read Independant reading sequence : –3.3V is not needed, chip has been reseted –Sensing circuitry detect the Efuse value –Burn shift register is loaded through the MUX –Data are serially outputted through the burn shift register Chip programming –As soon as sense circuitry has read out the fuse value, the data are loaded in the EFUSE register –In case of SEU, the data are automatically reloaded and an error flag is sent to the error block –It is possible to write custom value in the register, these value will be overwritten by the EFUSE value if sense is activated or if an SEU occurs

10. Read simulation 10 In that simulation, the values programmed in the efuse are sensed; an SEU is emulated to ensure that the values are automatically reloaded. A new set of value is programmed in the latches and a second SEU is simulated to check that the EFUSE values are correctly reloaded.

11. Spare slides

12. 12 One cell block IN OUT Burn_CK Ctrl_MUX Dburn Qburn from previous cell to next cell from/to internal memory EFUSE FCLRN FSETP Control the sense circuitry Control the efuse shift registerConnect to chip register

13. 13 One cell block (2) Dburn Qburn EFUSE Ctrl_Mux FCLRN FSETP Burn_CK Sense circuitry Write circuitry & DQ RN INOUT Ctrl_Mux Burn_CKBurn_RN Dburn Qburn FCLRN FSETP 1.5V 3.3V 1.5V  3.3V

14. 14 One cell block (3) The same shift register is used both for : –Writing token, ensuring that only one ’1’ is in the SR thus only one cell is programmed at a time –Reading out programmed data to ensure a correct programming independantly of the chip general memory

15. 15 Cell connection Qburn DFF SETN Burn_CK Dburn Qburn EFUSE Ctrl_Mux FCLRN FSETP Burn_CK RN EFUSE DFF This first cell ensures only one ‘1’ is in the SR during writing All other cells are standard EFUSE cells

16. Sense circuitry control Need to work without clock Start the sensing sequence and store the sensing result in the stand alone shift register.  Use of an asynchronous state machine 16 Sense Power on reset FCLRN FSETP MUX_CTRL LOAD SENSE ASM

17. State bit generation 17 Data ack. INOUT Release token SET RESET Delay rising ~ 30ns Delay falling < 5ns Q0Q0 Q1Q1 Q2Q2 Start cell Sense Power on reset

18. State bit generation 18 Sense Q0 Q1 Q2

19. Output bit generation 19 State bits Q0Q1Q2 FCLRN FSETP CTRL MUX LOAD Sequence take around 100ns to complete

20. 20 IBM Efuse specs © IBM

21. 21 Sensing circuitry © IBM

22. 22 Sensing chronogram © IBM

23. 23 Sensing output vs Efuse resistance